Clarion DRX6575RZ - CD Playback Modes; Scan, Repeat, and Random Play; Anti-Theft and Title Entry

MTC9462
051-6342-00
Digital servo for CD
1.Qutward Form : 100pins QFP
2.Function
3.Terminal Description
pin 1:
pin 2:
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
3:
>
20:
:COFS
> MONIT
23:
24:
25:
2
22
26:
27:
> PDO
> TMAX S
> TMAX
>LPFN
> LPF O
: PVref
: VCOret
: VCOF
> AVSS
>: SLCO
> RE IN
> AVDD
> RFCT
> RFZ)
: RFRP
> Fel
: SBAD
: TSIN
: TEI
: TEZ!
>FOO
>TRO
: Vref
> RFGC
> TEBC
:-FMO
-FVO
>: DMO
> 2Vref
> SEL
:FLG A
-FLG B
>FLGC
>FLGD
> VDD
-VSS
-100
-101
:102
-103
> DMQUT
> CKSE
: DACK
> TESIN
72:
73:
TESTO
HSO
UHSO
> EMPH
:LRCK
:VSS
:B CK
>A OUT
> D OUT
: MBOV
IPF
: SBOK
> CLOCK
>: VDD
:VSS
: DATA
-SF-SY
: SB SY
:SP CK
SP DA
VDD
TESIOO
P2Vref
HSSW
Z DET
TESIOI
vss
DRX6575Rz
000000! 0
151000 0 900}
oi;io!1!1o
z
: IN
=O
Oo oO
rs)
o0000
z
: Syna.separation,EFM, Error correction
> Not in use.
: Playback mode flag output. Ref. Table
1
: Playback mode flag output. Ref. Table
1
i Emphasis flag output of Sub cord Q da
ta."H"= emphasis ON.
: Channel clock output. (44.1kHz)
> Ground
: Bit clock output.(1.4122MHz)
: Audio data output.
: Digital output.
: Buffer memory over signal output.
: Compensation flag output.
: CRCC judgement output of Sub Q data.
"H*=OK.
: Clock output/input to read Sub cord
P to W.
: Positive supply voltage terminal.
: Ground.
: Sub cord P to W data output.
: Frame synchronize signal output.
: Sub cord block synchronize signe out
put.
: Clock signa! output to read processor
status.(176.4kHz)
: Processor status signa! output.
: Correction frame clock output.(7.35kHz)
: Not in use.
: Positive supply voltage terminal.
: Not in use.
: (Reference voltage) » 2 terminal for PLL
: pin26=Vref : x 2-speed or x 4-speed.
: 0 flag output of 1 bit DAC.
: Error signal output.(EFM-PLCK)
: TMAX detect signal output.
: TMAX detect signal output.
: Inverted input of amplifier for LPF.
: Output of amplher for LPF.
: Reference voltage terminal for PLL.
: Reference voltage terminal for VCO.
: Output of filter for VCO.
: Analog ground.
: Output of DAC for data slice level.
: RF signal input.
: Positive voltage supply for analog.
: Center level input of RFRP signal.
: RFRP O cross.
: RF ripple signal input.
: Focus error signal input.
: Sub beam addition signal input.
: Not in use.
: Tracking error input.
: Tracking error,O cross input.
: Focusing equalizer output.
: Tracking equalizer output.
: Reference voltage for analog.
: RF gain control signa! output.
: Tracking balance control signal output.
: Field equalizer output.
: Field error or Field search EQ output.
: Disc equalizer output.
: 2 x Vref for analog.
: Laser ON and UHS="H" : output"H”
: Monitor signal! output.
: Monitor signal output.
: Monitor signal output.
: Monitor signal output.
: Positive supply voltage.
: Ground.
> VO port.
> /O port.
> /O port.
: 1/0 port.
> Not in use.
> Not in use.
: Not in use.
: Not in use.
: Not in use.
: Ground.
pin 74:
pin 75:
pin 76:
pin 77:
pin 78:X1
pin 79:
pin 80:
pin 81:D
pin 82:R
pin 83: D
pin 84:D
pin 85: L
pin 86:
pin 87:
pin 88:
pin 89:
pin 90:
ping1:
pin 92:
pin 93:
pin 94:
pin 95:
pin 96:
pin 97:
pin 98:
pin 99:
pini00:
> IN
> IN
: IN
> VO:
:VO:
> VO
:VO:
> IN
> IN
> IN
> IN
> IN
: DSP oscillator input.
: DSP oscillator output.
: Positive supply voltage.
: Ground for system oscillator clock.
: System clock oscillator input.
: System clock oscillator output.
: Positive supply voltage for system clock
oscillator.
: Positive supply voltage for right channel DAC.
: Right channel data non-inverted output.
: Positive supply voltage for DAC.
: Reference voltage.
: Left channel data non-inverted output.
: Positive supply voltage for left channel DAC.
: Not in use.
: Not in use.
: Not in use.
Data bus to micro computer.
Data bus to micro computer.
:Data bus to micro computer.
Data bus to micro computer.
: Positive supply voltage.
> Ground.
: Clock input for data bus.
: Chip enable signal input. Negative logic.
: Not in use.
: Not in use.
: Reset signal input. Negative logic.
Table 1. Playback speed flag.
Piay back speed T UHSO(pin3) HSO(pin2)
Normal speed x 1 i H H
Normal speed x 2 | H be =
Normal speed x 4 | L H
Sea ese L L
-18-