5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG7
DEFENSIVE PULL DOWN SITE
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG4
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
DISPLAY PORT PRESENCE STRAP
CFG2
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PCIE PORT BIFURCATION STRAPS
CFG[0]: Stall reset sequence after PCU
Ʉ
PLL lock until de-asserted:
— 1 = (Default) Normal Operation;
No stall.
— 0 = Stall.
CFG[1]: Reserved configuration lane.
Ʉ
CFG[2]: PCI Express* Static x16 Lane
Ʉ
Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed.
CFG[3]: Reserved configuration lane.
Ʉ
CFG[4]: eDP enable:
Ʉ
— 1 = Disabled.
— 0 = Enabled.
CFG[6:5]: PCI Express* Bifurcation
Ʉ
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
Ʉ
— 1 = (default) PEG Train
immediately following RESET# de
assertion.
— 0 = PEG Wait for BIOS for
training.
CFG[19:8]: Reserved configuration
Ʉ
lanes.
TO EC
NEAR CPU
TO PCH-H
VCCST_PWRGD
CAD Note: Capacitor need to be placed
close to buffer output pin
Samuel change x16 01/05
Gary D02 reserved 0.1u to GND
VIDALERT#
PROCHOT#
H_PROCHOT#
VCCST_PWRGD_CPUVCCST_PWRGD
PM_DOWN
PECI
H_SKTOCC_N
H_TDO
H_TDI
H_TMS
H_TCK
H_TRST#
H_PREQ#
H_PRDY#
CFG_RCOMP
CFG0
CFG3
CFG4
CFG5
CFG6
CFG7
H_TDO
H_TCK
H_SKTOCC_N
CFG8
SYS_PWRGD#
VCCST_PWRGD
H_PROCHOT#
1.0V_VCCST
3.3VA
1.0V_VCCST
1.0V_VCCST
VDD3
1.0DX_VCCSTG
1.0DX_VCCSTG 6,56,58
VDD3 22,30,31,33,36,38,40,42,44,45,48,50,51,52,56,57,58,59,60,61,62,63
VCCIO 2,6,51,56
1.0V_VCCST 6,32,33,51,55
H_PROCHOT#55,58
PCH_CPU_BCLK_R_DN35
PCH_CPU_BCLK_R_DP35
PCH_CPU_PCIBCLK_R_DN35
PCH_CPU_PCIBCLK_R_DP35
CPU_24MHZ_R_DN35
CPU_24MHZ_R_DP35
H_PWRGD33
PLTRST_CPU_N32
H_PM_SYNC32
H_SKTOCC_N34
DDR_VTT_PG_CTRL53
H_CPU_SVIDCLK55
H_CPU_SVIDDAT55
H_CPU_SVIDALRT#55
PCH_THERMTRIP#32
PCH_PECI32
H_PM_DOWN32
H_PECI48
3.3VA 9,30,31,32,33,36,38,56
ALL_SYS_PWRGD28,31,48,55
H_PROCHOT_EC48
Title
Size Document Number Re v
Date: Sheet
of
6-71-N85P0-D02
D02
[04]Processor 4/7-CLK/JTAG/MISC
A3
471Monday, March 13, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Re v
Date: Sheet
of
6-71-N85P0-D02
D02
[04]Processor 4/7-CLK/JTAG/MISC
A3
471Monday, March 13, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Re v
Date: Sheet
of
6-71-N85P0-D02
D02
[04]Processor 4/7-CLK/JTAG/MISC
A3
471Monday, March 13, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
R464 *12.1_1%_04
R460 499_1%_04
R40
56.2_1%_04
R60 1K_04
C635
47P_50V_NPO_04
T99
SKYLAKE_HA LO
BGA1440
5 OF 14
REV = 1
?
?
U29E
QHPW
PROC_SELECT#
BN1
CATERR#
BM30
SKTOCC#
BR33
PM_DOWN
BP31
PM_SYNC
BM34
RESET#
BP35
PROCPWRGD
BT31
VCCST_PWRGD
H13
CFG[17]
BN23
CFG[15]
BT19
CFG[16]
BP23
CFG[11]
BT22
CFG[12]
BM19
CFG[10]
BT23
CFG[9]
BR22
CLK24N
D31
CFG[1]
BN27
CFG[3]
BN28
CFG[18]
BN22
PROC_TDI
BL32
CFG[0]
BN25
CFG[2]
BN26
CFG[4]
BR20
CFG[6]
BT20
CFG[5]
BM20
CFG[7]
BP20
CFG[8]
BR23
CFG[13]
BR19
CFG[14]
BP19
CFG[19]
BP22
PROC_PREQ#
BL30
PROC_PRDY#
BP27
VIDSCK
BH32
PROC_TDO
BT28
CLK24P
E31
PCI_BCLKN
C36
PCI_BCLKP
D35
BCLKN
A32
VIDSOUT
BH29
PROCHOT#
BR30
DDR_VTT_CNTL
BT13
CFG_RCOMP
BT25
PROC_TRST#
BP30
PROC_TCK
BR28
PROC_TMS
BP28
VIDALERT#
BH31
THERMTRIP#
J31
PECI
BT34
BCLKP
B31
BPM#[0]
BR27
BPM#[1]
BT27
BPM#[2]
BM31
BPM#[3]
BT30
S
D
G
Q36B
MTDK3S6R
5
34
R510
100K_04
C571
*0.1u_10V_X7R_04
R61
1K_04
C2202
*0.1u_10V_X7R_04
R91 *1K_04
R465 *0402_short
R62 60.4_1%_04
C570
*0.1u_10V_X7R_04
T96
R41
220_04
S
D
G
Q36A
MTDK3S6R
2
61
R430 20K_04
R509 *1K_04
T18
Q41
2SK3018S3
G
DS
R462 20_1%_04
R463 51_04
R484
49.9_1%_04
R429
100K_04
R483 51_04
R42
100_04
T98
R508 1K_04
R486 100K_04
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