5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PLEASE CLOSE TO CONNECTOR
PS8460B Repeter
To NV DP_F
DESIGN NOTE:PEQ
Programmalbe input equalization levels;internal pull
down at~150k ,3.3v I/O
L: default, LEQ, compensate channel loss up to 12dB at
HBR2
H: HEQ, compensate channel loss up to 15dB at HBR2
M:LLEQ, compensate channel loss up to 5dB at HBR2
AUX interception disable for Port y (y = 1, 2). Internal pull down at ~150K
㫉
, 3.3V I/O;
L: AUX interception enable, driver configuration is set by link training (default)
H: AUX interception disable, driver output with fixed 800mV and 0dB
M: AUX interception disable, driver output with fixed 400mV and 0dB
Output swing adjustment for Port y (y = 1, 2). Internal pull down at ~150K
㫉
, 3.3V I/O;
L: default
H: +20%
M: -16.7%
DESIGN NOTE:CFG0
Configuration pin for automatic EQ and
Aux interception; Internal pull down at
~150Kohm,3.3V I/O
L: default, automatic EQ enable and Aux interception enable
H: automatic EQ disable and AUX interception enable
M: automatic EQ disable and AUX interception
disable,no pre-emphasis, 600mVpp swing
DESIGN NOTE:CFG1
Configuration pin for auto test and input offset
cancellation,3 .3V IO, internal pull u p at~150K
H: default, auto test disable and input offset cancellation
ena bl e
L: auto test enable and input offset cancellation enable
M: auto test disable and input offset cancellation disable
Close to Display PORT
mini-Display Port E (LEFT)
ᶵ⎗ ⷞ
SY6288DAAC
㚫㺷 暣
CLOSE TO J_MDP2 CONN
1/14 NV CHECK
EMI
㒢㓦
3/23 lay
㰺䨢攻
,
㓡⮷
siz e
D02A
TO PS8460
1/5 NV CHECK
D02
D02
3/19 layout swap 3/19 layout swap
3/18
㍉岤⺢嬘ἧ䓐
20K V ES D
DP ESD W/O LEVELSHIFT
暨ᶲ
, NE T
⎗
SWAP
From NV DP_F
NV check 8/3
A1
⛐
dGPU
㗪
DD C /
AUX
㗗
Multiplax
PIN
Samuel 12/21
月 役
PIN46
月 役
PIN34
Gary D02 change to stuff
Gary PJ98 VDDQ change to 1.2VS
Gary D02 modify to combine Q72
Gary D02 modify to combine Q73
Co-LAY Co-LAY
SHORT
To NV DP_F
MDP_E3#_RE
MDP_E3_RE D_MDP_E3
D_MDP_E#3
G_MDPF_MODE
G_MDPF_CEC
D_MDP_E2J
D_MDP_E#2J
D_MDP_E3J
D_MDP_E#3J
D_MDP_E#0J
D_MDP_E0J
D_MDP_E#1J
D_MDP_E1J
DP_TDB_AUX#_F
DP_TDB_A UX_F
MDP_F _HPD_R
DP_TDB_A UX_F
DP_TDB_AUX#_F
G_DP_DHP D_F MDP_F _HPD_R
D_MDP_E#0J
D_MDP_E0J
D_MDP_E#0
D_MDP_E0
D_MDP_E#3J
D_MDP_E3J
D_MDP_E2J
D_MDP_E#2J
D_MDP_E2
D_MDP_E#2
D_MDP_E3
D_MDP_E#3
D_MDP_E#1J
D_MDP_E1J
D_MDP_E#1
D_MDP_E1
G_MDPF_MODE_R
G_DP_MODE_R
G_DP_MODE_R
G_MDPF_MODE
IN_L0P
IN_L0N
IN_L1P
IN_L1N
IN_L2P
IN_L2N
IN_L3P
IN_L3N
G_DP_DHP D_FMDP_E_HPD
MDP_E_HPD
EQ0
EQ1
CFG_0
DP_3.3V
DP_3.3V
DP_3.3V
DP_3.3V
MDP_E_HPD_RMDP_E_HPD
CFG1
DP_3.3V
DP_3.3V
CFG2
CSDAA
CSCLL
MDP_E0_RE
MDP_E0#_RE
MDP_E1_RE
MDP_E1#_RE
D_MDP_E1
D_MDP_E#1
MDP_E2_RE
MDP_E2#_RE
D_MDP_E2
D_MDP_E#2
VDD12
CSCLL
CSDAA
IN_L0P
IN_L0N
IN_L1P
IN_L1N
IN_L2P
IN_L2N
IN_L3P
IN_L3N
VDD33
VDDRX12
I2C_ADDRR
EQ1
EQ0
VDDRX12
VDDTX12
HPD_S NK
VDDTX12
VDDA1 2
VDDTX12
G_DP_DHP D_F
OUT_D0P
OUT_D0N
OUT_D1P
OUT_D1N
OUT_D2P
OUT_D2N
OUT_D3P
OUT_D3N
MDP_E0_RE
MDP_E0#_RE
MDP_E1_RE
MDP_E1#_RE
MDP_E2_RE
MDP_E2#_RE
MDP_E3_RE
MDP_E3#_RE
CFG2
CFG1
MDP_E_HPD_ R
VDD33
VDD12
MDP_E0_RE_LMDP_E0
MDP_E0#_RE_LMDP_E#0
MDP_E1_RE_LMDP_E1
MDP_E1#_RE_LMDP_E#1
MDP_E2_RE_LMDP_E2
MDP_E2#_RE_LMDP_E#2
MDP_E3_RE_LMDP_E3
MDP_E3#_RE_LMDP_E#3
CFG_0
VDD33 VDD12 VDDTX12 VDDA12
VDDRX12 VDDRX12
MDP_E0_RE
MDP_E0#_RE
MDP_E1_RE
MDP_E1#_RE
MDP_E2_RE
MDP_E2#_RE
MDP_E3_RE
MDP_E3#_RE
D_MDP_E#0
D_MDP_E0
DP_TDB_AUX#_F
DP_TDB_AUX_F
G_MDPF_MODE
3.3VS
MDP_F_PWR
EMI_G ND2
EMI_G ND2
MDP_F_PWR
MDP_F_PWR
MDP_F_PWR
MDP_F_PWR
5VS
5VS
1.2VS 1.2V
3.3VS DP _3.3V
DP_3.3V 1. 2V 1.2V 1.2V
1.2V 1.2V
MDP_E221
MDP_E#121
MDP_E121
MDP_E#221
MDP_E321
MDP_E021
MDP_E#321
MDP_E#021
SUSB26,29,45, 50
NV3V 310,22, 29,59,60,61, 63
3.3VS8,9,23, 26,28,29,30, 32,33,34,35, 36,38,40,41, 44,45,46,47, 48,49,50,55
5VS9,26, 29,45,47,48, 49,50,59,60
MDP_E_AUX_SCL21
MDP_E_AUX#_SDA21
MDP_E_HPD22,34
1.2VS29
Tit l e
Size
Document Num ber R e v
Date: Sheet
of
6-71-N85P0-D02
D02
[27] mDP (dGPU)
Cust om
27 71Monday, March 13, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEM ATIC1
Tit l e
Size
Document Num ber R e v
Date: Sheet
of
6-71-N85P0-D02
D02
[27] mDP (dGPU)
Cust om
27 71Monday, March 13, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEM ATIC1
Tit l e
Size
Document Num ber R e v
Date: Sheet
of
6-71-N85P0-D02
D02
[27] mDP (dGPU)
Cust om
27 71Monday, March 13, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEM ATIC1
C929 0.1u_10V_X7R_04
C2147 0.22u_10V_X5R_04
W/ 8460
C310 0. 22u_10V_X5R_04
W/ 8460
C2214 0. 1u_10V_X7R_04
W/o 8460
R1307 0_04
W/o 8460
T221
R1294 *4.7K _04
R1330
4.99K_1% _04
W/ 8460
R1301 0_04
W/o 8460
C2146 0.22u_10V_X5R_04
W/ 8460
R1290 0_04
W/ 8460
S
D
G
Q73B
MTDK3S6R
5
34
T222
R1308 0_04
W/o 8460
C21091u_6.3V_X5R_04
W/ 8460
C2087 0.22u_10V_X5R_04
W/ 8460
T223
C2149 0.22u_10V_X5R_04
W/ 8460
R825
10K_04
C894
0.01u_16V_X7R_04
R1302 0_04
W/o 8460
C21081u_6.3V_X5R_04
W/ 8460
R1395 *0_04
C885 0.1u_10V _X7R_04
W/o 8460
D69
BAV 99 RE CTIFIER
A
C
AC
C2148 0.22u_10V_X5R_04
W/ 8460
D67
*DT1140-04LP-7
5
1
2
3
4
10
9
8
7
6
C301 0. 22u_10V_X5R_04
W/ 8460
R795
1M_04
L72
*DVI2012F2SF-900T05_08-SHORT
1
4
2
3
U179
uP7549UMA5-20
PCB Foot print = M-SOT23-5
VOUT
1
VIN
5
GND
2
EN#
4
OC#
3
R1295 4.7K_04
W/ 8460
C2088 0.22u_10V_X5R_04
W/ 8460
C2150 0.22u_10V_X5R_04
W/ 8460
C2209 0. 1u_10V_X7R_04
W/o 8460
L64
FCM1005KF-121T03
W/ 8460
R1291 *4. 7K_04
R799 0_04
R1391 *0_04
S
D
G
Q74A
MTDK3S6R
2
61
C2208 0. 1u_10V_X7R_04
W/o 8460
R1396 *0_04
R1296 *4.7K _04
R1303 0_04
W/o 8460
D68
*DT1140-04LP-7
5
1
2
3
4
10
9
8
7
6
R794 5. 1M_04
W/ 8460
C2089 0.22u_10V_X5R_04
W/ 8460
C21311u_6.3V_X5R_04
W/ 8460
C888
*10u_6.3V_X5R_06
C2151 0.22u_10V_X5R_04
W/ 8460
R224
100K_1%_04
L70
*DVI2012F2SF-900T05_08-SHORT
1
4
2
3
R827
10K_04
C2210 0. 1u_10V_X7R_04
W/o 8460
C305 0. 22u_10V_X5R_04
W/ 8460
R1304 0_04
W/o 8460
R748 *0_04
R1289 0_04
W/o 8460
L68
FCM1005KF-121T03
W/ 8460
PS8460
U211
PS8460
W/ 8460
OUT_L3p
13
VDDTX12
14
OUT_L2n
15
OUT_L2p
16
HPD _SNK
17
OUT_L1n
18
OUT1p
19
DP_CA_DET
20
OUT_L0n
21
OUT_L0p
22
VDDTX12
23
VDD12
24
CFG2
1
CFG1
2
CFG0
3
HPD_SRC
4
VDD33
5
PD#
6
RSV0
7
REXT
8
VDD12
9
VDDTX12
10
VDDA12
11
OUT_L3n
12
EPAD
47
VDDRX12
46
IN_L3n
45
SDA_SRC
31
IN_AUXp
30
IN_AUXn
29
OUT_AUXp
28
OUT_AUXn
27
CSCL
26
CSDA
25
I2C_ADDR
37
IN_L1p
38
IN_L1n
39
EQ1
40
IN_L2p
41
IN_L2n
42
EQ0
43
IN_L3p
44
IN_L0p
35
VDDRX12
34
IN_L0n
36
VDD33
33
SCL_SRC
32
S
D
G
Q72A
MTDK3S6R
2
6 1
L67
FCM1005KF-121T03
W/ 8460
C2152 0.22u_10V_X5R_04
W/ 8460
R1392 *0_04
L65
FCM1005KF-121T03
W/ 8460
EMR10 0_04
C2090 0.22u_10V_X5R_04
W/ 8460
12
20
13
15
10
8
4
3
16
2
6
14
18
1
5
7
9
11
19
17
COMMO N
C17714-101
J_MDP2
PCB Foot print = C17714-120A8-L
1
GND
HPD
2
3
LANE_0P
4
CONFIG1 LANE_0N
5
6
CONFIG2
7
GND
GND
8
9
LANE_1P
10
LANE_3P LANE_1N
11
12
LANE_3N
GND
13
GND
14
15
LANE_2P
AUX_CHP
16
17
LANE_2N
18
AUX_CHN
GND
19
PWR
20
SHIELD6
GND4
SHIELD5
GND3
GND2
SHIELD2
GND1
SHIELD1
R1329 0_04
W/ 8460
C889
10u_6.3V_X5R_06
L69
*DVI2012F2SF-900T05_08-SHORT
1
4
2
3
C2211 0. 1u_10V_X7R_04
W/o 8460
A
A
C
D66
BAT54CS3
1
2
3
C21251u_6.3V_X5R_04
W/ 8460
R1297 *4. 7K_04
C300 0. 22u_10V_X5R_04
W/ 8460
C21131u_6.3V_X5R_04
W/ 8460
S
D
G
Q72B
MTDK3S6R
5
34
PJ98
OPEN_1mm
1 2
L66
FCM1005KF-121T03
W/ 8460
R744 *0_04
R1305 0_04
W/o 8460
R219
100K_1%_04
C21261u_6.3V_X5R_04
W/ 8460
R1292 *4. 7K_04
C2212 0. 1u_10V_X7R_04
W/o 8460
S
D
G
Q74B
MTDK3S6R
5
34
R1393 *0_04
C928 0.1u_10V_X7R_04
C21031u_6.3V_X5R_04
W/ 8460
R1298 *4. 7K_04
R1306 0_04
W/o 8460
C933
0.01u_16V_X7R_04
EMR6 0_04
L61
FCM1005KF-121T03
C21201u_6.3V_X5R_04
W/ 8460
L71
*DVI2012F2SF-900T05_08-SHORT
1
4
2
3
C2213 0. 1u_10V_X7R_04
W/o 8460
R1265
0_04
L63
FCM1005KF-121T03
W/ 8460
C2145 0.22u_10V_X5R_04
W/ 8460
C909
220p_50V_NPO_04
PJ99
OPEN_1mm
1 2
S
D
G
Q73A
MTDK3S6R
2
6 1
R1293 *4.7K _04
R1394 *0_04
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