5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG7
DEFENSIVE PULL DOWN SITE
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG4
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
DISPLAY PORT PRESENCE STRAP
CFG2
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PCIE PORT BIFURCATION STRAPS
CFG[0]: Stall reset sequence after PCU PLL
Ʉ
lock until de-asserted:
— 1 = (Default) Normal Operation; No
stall.
— 0 = Stall.
CFG[1]: Reserved configuration lane.
Ʉ
CFG[2]: PCI Express* Static x16 Lane
Ʉ
Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed.
CFG[3]: Reserved configuration lane.
Ʉ
CFG[4]: eDP enable:
Ʉ
— 1 = Disabled.
— 0 = Enabled.
CFG[6:5]: PCI Express* Bifurcation
Ʉ
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
Ʉ
— 1 = (default) PEG Train immediately
following RESET# de assertion.
— 0 = PEG Wait for BIOS for training.
CFG[19:8]: Reserved configuration lanes.
Ʉ
TO EC
NEAR CPU
TO PCH-H
VCCST_PWRGD
CAD Note: Capacitor need to be placed
close to buffer output pin
Configuration Signals: The CFG signals have a
default value of '1' if not terminated on the board.
Refer to the appropriate platform design guide for
pull-down recommendations when a logic low is
desired.
1.05DX_VCCSTG
3.3VA
1.05V_VCCST
1.05V_VCCST
VDD3
1.05DX_VCCSTG
1.05DX_VCCSTG 6,33,53
VDD3 23,30,31,33,36,39,40,42,44,45,46,47,48,49,52,53,55,56,57,58,59,60,63,70,71,72
1.05V_VCCST 6,32,48,52
H_PROCHOT#52
PCH_CPU_BCLK_R_DN35
PCH_CPU_BCLK_R_DP35
PCH_CPU_PCIBCLK_R_DN35
PCH_CPU_PCIBCLK_R_DP35
CPU_24MHZ_R_DN35
CPU_24MHZ_R_DP35
H_PWRGD33
PLTRST_CPU_N32
H_PM_SYNC32
H_SKTOCC_N34,38
DDR_VTT_PG_CTRL50
H_CPU_SVIDCLK52
H_CPU_SVIDDAT52
H_CPU_SVIDALRT#52
PCH_THERMTRIP#32
PCH_PECI32
H_PM_DOWN32
H_PECI45
3.3VA 30,31,32,33,36,38,44,48,53
ALL_SYS_PWRGD28,31,45,52
H_PROCHOT_EC45
VCCIO 2,6,48
H_TCK 33
H_TMS 33
H_TDO 33
H_TDI 33
H_TRST# 38
H_PREQ# 38
H_PRDY# 38
Title
Size Document Number Rev
Date: Sheet
of
6-71-NH5D0-D02
D02
[04]Processor 4/7-CLK/JTAG/MISC
A3
474Tuesday, February 18, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-NH5D0-D02
D02
[04]Processor 4/7-CLK/JTAG/MISC
A3
474Tuesday, February 18, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-NH5D0-D02
D02
[04]Processor 4/7-CLK/JTAG/MISC
A3
474Tuesday, February 18, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
R621 *12.1_1%_04
T22
R582 *1K_04
R603 499_1%_04
R516
56.2_1%_04
R604 1K_04
T96
C1039
47p_25V_NPO_02
T25
S
D
G
Q58B
MTDK3S6R
5
34
R592
100K_04
T99
C1032
*0.1u_10V_X7R_04
T97
T98
R581
1K_04
C302
*0.1u_10V_X7R_04
T95
5 OF 13
?
?
?
U37E
CML_H_IP_EXT/BGA
VIDSOUT
BH29
DDR_VTT_CNTL
BT13
VCCST_PWRGD
H13
PM_SYNC
BM34
PM_DOWN
BP31
PECI
BT34
CFG_18
BN22
PROC_TCK
BR28
CFG_19
BP22
THERMTRIP#
J31
PROC_TDO
BT28
CFG_0
BN25
PROC_TRST#
BP30
CFG_1
BN27
PROC_SELECT#
BN1
ZVM#
AT13
SKTOCC#
BR33
CFG_2
BN26
CFG_RCOMP
BT25
CFG_3
BN28
PROC_PREQ#
BL30
CFG_4
BR20
CFG_10
BT23
RESET#
BP35
CFG_5
BM20
CLK24N
D31
PROCPWRGD
BT31
CFG_11
BT22
CFG_6
BT20
BPM#_0
BR27
VIDSCK
BH32
BCLKN
A32
PCI_BCLKN
C36
BPM#_1
BT27
CFG_7
BP20
CFG_12
BM19
CLK24P
E31
CFG_8
BR23
CFG_13
BR19
BPM#_2
BM31
BCLKP
B31
PCI_BCLKP
D35
BPM#_3
BT30
PROCHOT#
BR30
CFG_9
BR22
CFG_14
BP19
RSVD2
AY13
CFG_15
BT19
RSVD1
AU13
PROC_PRDY#
BP27
CFG_16
BP23
CATERR#
BM30
PROC_TDI
BL32
MSM#
AW13
PROC_TMS
BP28
CFG_17
BN23
VIDALERT#
BH31
R578 60.4_1%_04
R622 *0402_short
C1030
*0.1u_10V_X7R_04
R141
220_04
S
D
G
Q58A
MTDK3S6R
2
61
R589 20K_04
R600 20_1%_04
Q59
2SK3018S3
G
DS
R562 100_04
R155
49.9_1%_04
R591
100K_04
T24
R623 51_04
R146 51_04
R624 51_04
R150
100_04
T23
T26
R599 100K_04
R587 1K_04
VIDALERT#
PROCHOT#
H_PROCHOT#
VCCST_PWRGD_CPUVCCST_PWRGD
PM_DOWN
PECI
H_SKTOCC_N
H_TDO
H_TDI
H_TMS
H_TCK
H_TRST#
H_PREQ#
H_PRDY#
CFG_RCOMP
CFG0
CFG3
CFG4
CFG5
CFG6
CFG7
H_TDO
H_TCK
H_SKTOCC_N
CFG8
SYS_PWRGD#
VCCST_PWRGD
H_PROCHOT#
CFG_1
CFG9
CFG11
CFG14
CFG15
H_TDI
H_TMS