Clevo NL40MU1 - Processor 2;12

Schematic Diagrams
B - 4 Processor 2/12
B.Schematic Diagrams
Processor 2/12
Sheet 3 of 47
Processor 2/12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SINGLE=50ohm
DATA
CMD
SINGLE=45ohm
SINGLE=45ohm
CTRL
SINGLE=50ohm
DIFF=90ohm
STROBE
CTRL
SINGLE=45ohm
CLOCK
DIFF=85ohm
A0
M_A_A1
M_A_A0
M_A_A3
M_A_A4
M_A_A2
M_A_A5
M_A_A6
M_A_A7
M_A_A9
M_A_A10
M_A_A12
M_A_A11
M_A_A8
M_A_A16
M_A_A13
M_A_A14
M_A_A15
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS3
M_A_DQS1
M_A_DQS7
M_A_DQS#7
M_A_DQS#6
M_A_DQS6
M_A_DQS5
M_A_DQS4
M_A_DQS#3
M_A_DQS#1
M_A_DQS#2
M_A_DQS2
M_A_DQS0
M_A_DQS#0
M_A_DQS#5
M_A_DQS#4
DDR_RCOMP_0
M_A_DQ_0_0[14]
M_A_DQ_1_0[14]
M_A_DQ_1_1[14]
M_A_DQ_1_2[14]
M_A_DQ_1_3[14]
M_A_DQ_1_4[14]
M_A_DQ_1_5[14]
M_A_DQ_1_6[14]
M_A_DQ_1_7[14]
M_A_DQ_0_1[14]
M_A_DQ_0_2[14]
M_A_DQ_0_3[14]
M_A_DQ_0_4[14]
M_A_DQ_0_5[14]
M_A_DQ_0_6[14]
M_A_DQ_0_7[14]
M_A_DQ_2_0[14]
M_A_DQ_2_1[14]
M_A_DQ_2_2[14]
M_A_DQ_2_3[14]
M_A_DQ_2_4[14]
M_A_DQ_2_5[14]
M_A_DQ_2_6[14]
M_A_DQ_2_7[14]
M_A_DQ_3_0[14]
M_A_DQ_4_0[14]
M_A_DQ_5_0[14]
M_A_DQ_3_1[14]
M_A_DQ_3_2[14]
M_A_DQ_3_3[14]
M_A_DQ_3_4[14]
M_A_DQ_3_5[14]
M_A_DQ_3_6[14]
M_A_DQ_3_7[14]
M_A_DQ_4_1[14]
M_A_DQ_4_2[14]
M_A_DQ_4_3[14]
M_A_DQ_4_4[14]
M_A_DQ_4_5[14]
M_A_DQ_4_6[14]
M_A_DQ_4_7[14]
M_A_DQ_6_0[14]
M_A_DQ_7_0[14]
M_A_DQ_5_1[14]
M_A_DQ_5_2[14]
M_A_DQ_5_3[14]
M_A_DQ_5_4[14]
M_A_DQ_5_5[14]
M_A_DQ_5_6[14]
M_A_DQ_5_7[14]
M_A_DQ_6_1[14]
M_A_DQ_6_2[14]
M_A_DQ_6_3[14]
M_A_DQ_6_4[14]
M_A_DQ_6_5[14]
M_A_DQ_6_6[14]
M_A_DQ_6_7[14]
M_A_DQ_7_1[14]
M_A_DQ_7_2[14]
M_A_DQ_7_3[14]
M_A_DQ_7_4[14]
M_A_DQ_7_5[14]
M_A_DQ_7_6[14]
M_A_DQ_7_7[14]
M_A_A[16:0] [14]
M_A_ODT1 [14]
M_A_ODT0 [14]
M_A_DQS#[7:0] [14]
M_A_DQS[7:0] [14]
M_A_BG1 [14]
M_A_BG0 [14]
M_A_BA0 [14]
M_A_BA1 [14]
DDR0_A_ALERT# [14]
M_A_ACT# [14]
DDR0_A_PARITY [14]
DDR0_VREF_CA [14]
DDR_VTT_CTRL [31]
CPUDRAMRST# [14,15]
M_A_CLK_DDR0 [14]
M_A_CLK_DDR#0 [14]
M_A_CLK_DDR#1 [14]
M_A_CLK_DDR1 [14]
M_A_CKE0 [14]
M_A_CKE1 [14]
M_A_CS#1 [14]
M_A_CS#0 [14]
Title
Size Document Number Re v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[03] TGL U -B / DDR CHA
A3
347Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Re v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[03] TGL U -B / DDR CHA
A3
347Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Re v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[03] TGL U -B / DDR CHA
A3
347Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
U21B
TGL_U_IP_EXT
DDR0_ALERT#
AU50
?
DDR0_VREF_CA
AU49
DDR_VTT_CTL
E52
DDR_RCOMP
C49
DDR0_BG0/DDR2_CA3/DDR2_CA4/DDR2_CS1
BL52
DDR0_MA5/DDR0_CA5/DDR0_CA6/DDR0_CA0
BY50
DDR0_ODT1/DDR1_CA0/DDR1_CA0/DDR1_CA6
CF44
DDR0_CKE1/DDR2_CA4/DDR2_CA5/DDR2_CA1
BU52
NC/DDR1_CKE0/DDR1_WCK_P/DDR1_WCK_P
CD45
DDR3_DQ1_0/DDR0_DQ7_0/DDR1_DQ3_0
BD41
DDR3_DQ1_5/DDR0_DQ7_5/DDR1_DQ3_5
BD45
DDR3_DQ0_0/DDR0_DQ6_0/DDR1_DQ2_0
BH41
DDR3_DQ0_5/DDR0_DQ6_5/DDR1_DQ2_5
BH47
DDR2_DQ1_0/DDR0_DQ5_0/DDR0_DQ3_0
BC49
DDR2_DQ1_5/DDR0_DQ5_5/DDR0_DQ3_5
AY50
DDR2_DQ0_0/DDR0_DQ4_0/DDR0_DQ2_0
BH49
DDR2_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5
BF50
DDR1_DQ1_0/DDR0_DQ3_0/DDR1_DQ1_0
CK41
DDR1_DQ1_5/DDR0_DQ3_5/DDR1_DQ1_5
CK45
DDR1_DQ0_0/DDR0_DQ2_0/DDR1_DQ0_0
CV41
DDR1_DQ0_5/DDR0_DQ2_5/DDR1_DQ0_5
CT45
DDR0_DQ1_0/DDR0_DQ1_0/DDR0_DQ1_0
CL49
DDR0_DQ1_5/DDR0_DQ1_5/DDR0_DQ1_5
CH50
DDR0_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0
CU49
DDR0_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5
CP50
DDR3_DQ1_3/DDR0_DQ7_3/DDR1_DQ3_3
BB42
DDR3_DQ0_3/DDR0_DQ6_3/DDR1_DQ2_3
BH42
DDR2_DQ1_3/DDR0_DQ5_3/DDR0_DQ3_3
BC53
DDR2_DQ0_3/DDR0_DQ4_3/DDR0_DQ2_3
BH53
DDR1_DQ1_3/DDR0_DQ3_3/DDR1_DQ1_3
CK42
DDR1_DQ0_3/DDR0_DQ2_3/DDR1_DQ0_3
CT42
DDR0_DQ1_3/DDR0_DQ1_3/DDR0_DQ1_3
CL53
DDR0_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3
CU53
DDR0_BA0/DDR3_CA0/DDR3_CA0/DDR3_CA6
BV44
DDR0_MA2/DDR3_CS0/DDR3_CA2/DDR3_CA2
BV47
DDR0_MA11/NC/DDR2_CS1/DDR2_CA4
BT51
DDR0_MA3/DDR0_CS1/DDR0_CS0/DDR0_CA3
CD53
DDR0_CS1/DDR1_CA1/DDR1_CA1/DDR1_CA5
CF42
DDR3_DQ1_1/DDR0_DQ7_1/DDR1_DQ3_1
BD42
DDR3_DQ1_2/DDR0_DQ7_2/DDR1_DQ3_2
BB41
DDR3_DQ1_6/DDR0_DQ7_6/DDR1_DQ3_6
BB47
DDR3_DQ1_7/DDR0_DQ7_7/DDR1_DQ3_7
BD47
DDR3_DQ0_1/DDR0_DQ6_1/DDR1_DQ2_1
BK41
DDR3_DQ0_2/DDR0_DQ6_2/DDR1_DQ2_2
BK42
DDR3_DQ0_6/DDR0_DQ6_6/DDR1_DQ2_6
BK45
DDR3_DQ0_7/DDR0_DQ6_7/DDR1_DQ2_7
BK47
DDR2_DQ1_1/DDR0_DQ5_1/DDR0_DQ3_1
BC50
DDR2_DQ1_2/DDR0_DQ5_2/DDR0_DQ3_2
BC52
DDR2_DQ1_6/DDR0_DQ5_6/DDR0_DQ3_6
AY52
DDR2_DQ1_7/DDR0_DQ5_7/DDR0_DQ3_7
AY53
DDR2_DQ0_1/DDR0_DQ4_1/DDR0_DQ2_1
BH50
DDR2_DQ0_2/DDR0_DQ4_2/DDR0_DQ2_2
BH52
DDR2_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6
BF52
DDR2_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7
BF53
DDR1_DQ1_1/DDR0_DQ3_1/DDR1_DQ1_1
CM41
DDR1_DQ1_2/DDR0_DQ3_2/DDR1_DQ1_2
CM42
DDR1_DQ1_6/DDR0_DQ3_6/DDR1_DQ1_6
CM47
DDR1_DQ1_7/DDR0_DQ3_7/DDR1_DQ1_7
CK47
DDR1_DQ0_1/DDR0_DQ2_1/DDR1_DQ0_1
CT41
DDR1_DQ0_2/DDR0_DQ2_2/DDR1_DQ0_2
CV42
DDR1_DQ0_6/DDR0_DQ2_6/DDR1_DQ0_6
CV47
DDR1_DQ0_7/DDR0_DQ2_7/DDR1_DQ0_7
CT47
DDR0_DQ1_1/DDR0_DQ1_1/DDR0_DQ1_1
CL50
DDR0_DQ1_2/DDR0_DQ1_2/DDR0_DQ1_2
CL52
DDR0_DQ1_6/DDR0_DQ1_6/DDR0_DQ1_6
CH52
DDR0_DQ1_7/DDR0_DQ1_7/DDR0_DQ1_7
CH53
DDR0_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1
CU50
DDR0_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2
CU52
DDR0_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6
CP52
DDR0_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7
CP53
DDR0_BA1/DDR1_CA5/DDR1_CA6/DDR1_CA0
CB42
DDR0_MA0/NC/DDR3_CS1/DDR3_CA4
BV41
DDR0_MA8/DDR0_CA2/DDR0_CA3/DDR0_CS0
BY53
NC/DDR3_CKE0/DDR3_WCK_P/DDR3_WCK_P
BT45
DDR0_PAR/DDR3_CS1/DDR3_CS0/DDR3_CA3
BV45
NC/DDR3_CA2/DDR3_CA3/DDR3_CS0
BP44
NC/DDR3_CA3/DDR3_CA4/DDR3_CS1
BP45
DDR0_MA9/DDR2_CA0/DDR2_CA0/DDR2_CA6
BU50
DDR0_MA13/DDR1_CS1/DDR1_CS0/DDR1_CA3
CF41
NC/DDR3_CA4/DDR3_CA5/DDR3_CA1
BP42
NC/DDR3_CA5/DDR3_CA6/DDR3_CA0
BP47
NC/DDR2_CKE0/DDR2_WCK_P/DDR2_WCK_P
BN51
DDR0_MA10/DDR3_CA1/DDR3_CA1/DDR3_CA5
BV42
DDR0_MA15/DDR1_CA3/DDR1_CA4/DDR1_CS1
CB44
DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0
CR51
DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1
CK51
DDR1_DQSP_0/DDR0_DQSP_2/DDR1_DQSP_0
CT44
DDR1_DQSP_1/DDR0_DQSP_3/DDR1_DQSP_1
CK44
DDR2_DQSP_0/DDR0_DQSP_4/DDR0_DQSP_2
BG51
DDR2_DQSP_1/DDR0_DQSP_5/DDR0_DQSP_3
BA51
DDR3_DQSP_0/DDR0_DQSP_6/DDR1_DQSP_2
BK44
DDR3_DQSP_1/DDR0_DQSP_7/DDR1_DQSP_3
BB44
NC/DDR0_CA1/DDR0_CA1/DDR0_CA5
CE50
NC/DDR0_CA0/DDR0_CA0/DDR0_CA6
CE53
DDR0_CKE0/DDR2_CA5/DDR2_CA6/DDR2_CA0
BL50
NC/DDR0_CKE1/DDR0_WCK_N/DDR0_W CK
CA53
NC/DDR1_CKE1/DDR1_WCK_N/DDR1_W CK
CD47
NC/DDR2_CKE1/DDR2_WCK_N/DDR2_W CK
BN53
NC/DDR3_CKE1/DDR3_WCK_N/DDR3_W CK
BT47
NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P
BP52
DDR0_BG1/DDR2_CA2/DDR2_CA3/DDR2_CS0
BN50
DDR0_MA1/NC/DDR0_CS1/DDR0_CA4
CE52
DDR0_MA4/DDR0_CS0/DDR0_CA2/DDR0_CA2
CD51
DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0
CR50
DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1
CK50
DDR1_DQSN_0/DDR0_DQSN_2/DDR1_DQSN_0
CV44
DDR1_DQSN_1/DDR0_DQSN_3/DDR1_DQSN_1
CM44
DDR2_DQSN_0/DDR0_DQSN_4/DDR0_DQSN_2
BG50
DDR2_DQSN_1/DDR0_DQSN_5/DDR0_DQSN_3
BA50
DDR3_DQSN_0/DDR0_DQSN_6/DDR1_DQSN_2
BH44
DDR3_DQSN_1/DDR0_DQSN_7/DDR1_DQSN_3
BD44
NC/DDR2_CLK_N/DDR2_CLK_N/DDR2_CLK
BP53
DDR0_ACT#/DDR2_CS1/DDR2_CS0/DDR2_CA3
BT53
DDR0_MA16/DDR1_CA4/DDR1_CA5/DDR1_CA1
CB47
DDR0_MA7/DDR0_CA4/DDR0_CA5/DDR0_CA1
CA50
NC/DDR2_CS0/DDR2_CA2/DDR2_CA2
BL53
NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P
CD42
DDR0_ODT0/DDR1_CS0/DDR1_CA2/DDR1_CA2
CF45
DDR0_CLK_N0/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK
CC53
DDR0_CLK_N1/DDR3_CLK_N/DDR3_CLK_N/DDR3_CLK
BT41
NC/DDR0_CKE0/DDR0_WCK_P/DDR0_WCK_P
CA51
DDR0_CLK_P0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P
CC52
DDR0_MA12/DDR2_CA1/DDR2_CA1/DDR2_CA5
BU53
DDR0_MA14/DDR1_CA2/DDR1_CA3/DDR1_CS0
CB45
DDR0_CS0/NC/DDR1_CS1/DDR1_CA4
CF47
NC/DDR1_CLK_N/DDR1_CLK_N/DDR1_CLK
CD41
DDR0_CLK_P1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P
BT42
DDR3_DQ1_4/DDR0_DQ7_4/DDR1_DQ3_4
BB45
DDR3_DQ0_4/DDR0_DQ6_4/DDR1_DQ2_4
BH45
DDR2_DQ1_4/DDR0_DQ5_4/DDR0_DQ3_4
AY49
DDR2_DQ0_4/DDR0_DQ4_4/DDR0_DQ2_4
BF49
DDR1_DQ1_4/DDR0_DQ3_4/DDR1_DQ1_4
CM45
DDR1_DQ0_4/DDR0_DQ2_4/DDR1_DQ0_4
CV45
DDR0_DQ1_4/DDR0_DQ1_4/DDR0_DQ1_4
CH49
DDR0_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4
CP49
DRAM_RESET#
DV47
DDR0_MA6/DDR0_CA3/DDR0_CA4/DDR0_CS1
BY52
R21
100_1%_04