EasyManua.ls Logo

Commodore Computers 1581 - 8520 A CIA Interface Details; Interface Signals and Their Roles

Default Icon
22 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
1581
SERVICE
MANUAL
8520A
COMPLEX
INTERFACE
ADAPTER
vss-
PAO-
PA1-
PA2-
PA3-
PA4-
PA5-
PA6-
PA7-
PBO-
PB1-
PB2-
PB3-
PB4-
PB5-
PB6-
PB7-
PC-
TOD-
VCC-
1
2
3
4
CJI
6
7
8
9
10
8520
11
CIA
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
-CNT
-SP
-RSO
-RS1
-RS2
-RS3
-RES
-DBO
-DB1
-DB2
-DB3
-DB4
-DB5
-DB6
-DB7
-02
-FLAG
-CS
-R/W
-IRQ
INTERFACE
SIGNALS
02
Clock
Input
The
02
clock
is
a
TTL,
compatible
input
used
for
internal
device
operation
and
as
a
timing
reference
for
communicating
with
the
system
data
bus.
CS
Chip
Select
Input
The
CS
input
controls
the
activity
of
the
8520.
A
low
level
on
CS
while
02
is
high
causes
the
device
to
respond
to
signals
on
the
R/W
and
address
(RS)
lines.
A
high
on
CS
prevents
these
lines
from
controlling
the
8520.
The
CS
line
is
normally
activated
(low)
at
02
by
the
appropriate
address
combination.
R/W—Read/Write
Input
The
R/W
signal
is
normally
supplied
by
the
microprocessor
and
controls
the
direction
of
data
transfers
of
the
8520.
A
high
on
R/W
indicates
a
read
(data
transfer
out
of
the
8520),
while
a
low
indicates
a
write
(data
transfer
into
the
8520).
RS3-RS0
Address
Inputs
The
address
inputs select
the
internal
registers
as
described
by
the
Register
Map.
DB7-DB0
Data
Bus
Inputs/Outputs
The
eight
bit
data
bus
transfers
information
between
the
8520
and
the
system
data
bus.
These
pins
are
high
impedance
inputs
unless
CS
is
low
and
R/W
and
02
are
high,
to
read
the
device.
During
this
read,
the
data
bus
output
buffers
are
enabled,
driving
the
data
from
the
selected
register
onto
the
system
data
bus.
IRQ
Interrupt
Request
Output
IRQ
is
an
open
drain
output
normally
connected
to
the
processor
interrupt
input.
An
external
pullup
resistor
holds
the
signal
high,
allowing
multiple
IRQ-outputs
to
be
connected
together
The
IRQ
output
is
normally
off
(high
impedance)
and
is
activated
low
as
indicated
in
the
functional
description.
RES
Reset
Input
A
low
on
the
RES
pin
resets
all
internal
registers.
The
port
pins
are
set
as
inputs
and
port
registers
to
zero
(although
a
read
of
the
ports
will
return
all
highs
because
of
passive
pullups)
The
timer
control
registers
are
set
to
zero
and
the
timer
latches
to
all
ones.
All
other
registers
are
reset
to
zero