Commodore Computers 1581 - Processor Interface and Operations

1581 SERVICE MANUAL
Arithmetic/Logic Unit (ALU) — The ALL) is a serial comparator, incrementor, and decrementor, and is used for register
modification and comparisons with the disk recorded ID field.
Timing and Control — All computer and Floppy Disk interface controls are generated through this logic. The internal
device timing is generated from an external crystal clock. The FD1770 has two different modes of operation according
to the state of DDEN. When DDEN = 0, double density (MFM) is enabled. When DDEN = 1, single density is enabled.
AM Detector — The address mark detector detects ID, data and index address marks during read and write operations.
Data Separator— A digital data separator, consisting of a ring shift register and data window detection logic, provides
read data and a recovery clock to the AM detector.
PROCESSOR INTERFACE
The interface to the processor is accomplished through the eight Data Access Lines (DAL) and associated control signals.
The DAL are used to transfer Data, Status, and Control words_out of, orjnto the WD1770. The DAL are three state
buffersjhat are enabled as output drivers when Chip Select (CS) and R/W = 1 are active or act as imput receivers
when CS and R/W = 0 are active.
When transfer of data with the Floppy Disk Controller is required by the host processoMhe device address is decoded
and CS is made low. The address bits A1 and AO, combined with the signal R/W, during a Read operation or
Write operation are interpreted as selecting the following registers:
A1 - AO
0 0
0 1
1 0
1 1
Read (R/W= 1)
Status Register
Track Register
Sector Register
Data Register
WRITE (R/W= 0)
Command Register
Track Register
Sector Register
Data Register
During Direct Memory Access (DMA) types of data transfers between the Data Register of the WD1770 and the pro
cessor, the Data Request (DRQ) output is used in Data Transfer control. This signal also appears as status bit 1 during
Read and Write operations.
On Disk Read operations, the Data Request is activated (set high) when an assembled serial input byte is transferred
in parallel to the Data Register. This bit is cleared when the Data Register is read by the processor. If the Data Register
is read after one or more characters are lost, by having new data transferred into the register prior to processor readout,
the Lost Data bit is set in the Status Register. The Read operation continues until the end of sector is reached.
On Disk Write operations, the Data Request is activated when the Data Register transfers its contents to the Data Shift
Register, and requires a new data byte. It is reset when the Data Register is loaded with new data by the processor.
If new data is not loaded at the time the next serial byte is required by the Floppy Disk, a byte of zeroes is written on
the diskette and the Lost Data is set in the Status Register.
At the completion of every command, an INTRQ is generated. INTRQ is reset by either reading the status register,
or by loading the command register with a new command. In addition, INTRQ is generated if a Force Interrupt com
mand condition is met.
The WD1770 has two modes of operation according to the state DDEN (Pin 26). When DDEN = 1, single density is
selected. In either case, the CLK input (Pin 18) is at 8 MHZ.
UJ
o
<
Li-
CC
UJ
HOST
CK
CS
R/W
MR _
; DRQ
INTRQ
+ 5
Jdden i
GND VCC
WG
WD
RD
^TROO
WPRT
MO
DIRC
' + 5 V.
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