The design that has gone into this aspect of the controller has been
to enhance performance and increase flexibility while reducing cost.
As a result, the majority of operations have been placed in firmware.
The only functions performed by "hardware" are those that are too
fast for the processor.
The
Z80A CPU and
its
associated PROM and RAM collectively per-
form the following functions:
1.
Power up initialization
2. Diagnostics
3.
Error recovery
4.
Error reporting
5.
Error correction
6. Command processor
7.
Disk select
8. Seek
9.
Write precomp select, reduced write current
10. Head select
11. Mapping
12. Logical to physical address translation
Physical to logical address translation
The
DJC
Custom
Chip
The DJC is a custom LSI chip.
It
has been designed to handle all serial
data, state machine and DMA functions as described below:
ERROR CORRECTION CODE
The error correction polynomial is a 32-bit code capable of correct-
ing up to l
l
-bit burst errors.
In keeping with the overall design philosophy, the ECC circuitry gen-
erates the write syndrome and validates the read without requiring
the processor to handle the data. Calculating this polynomial with the
processor would seriously degrade the performance of the
ST506
controller. Calculating the reverse polynomial to correct bad data
is
done by the processor.
It
is accomplished without any measurable ef-
fect on performance because the operation is only done after multi-
ple retries and as such is seldom necessary.
HEADER VERIFICATION
Once a disk has been formatted, the DJC converts the desired record
address on the disk. The conversion
is
done in terms of head, track
and sector address, with a CRC code tested to further insure
posi-
tional integrity.
A
comparison
is
then made of the header before a
read or write function is performed.
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