Table
6-1
Pin Description
PIN PIN SIGNAL
NAME NUMBER DIRECTION DESCRIPTION
A19-A1 59 thru
77
IN
Address busAl to
A8
are used by the processor to
select the internal registers and put an address code
on the
RGA
lines to select registers outside the device.
The processor uses
At to A1
8
to generate multi-
plexed
DRAM
addresses on the
MA
outputs. The A1
9
line is used to indicate which RAS line is activated.
If
A1
9
is high, RASl* is asserted;
if
low, RASO* is as-
serted.
RD1
5-RDO
1
thru
14
110
and
83
&
84
AS* 24
IN
RGEN* 23
IN
RAMEN* 25
IN
PRW 22
IN
RRW
2 1 OUT
This data bus is buffered and is used by the processor
to access the device registers. The data bus is also
ac-
cessed during
DMA
operations.
Active low. This input is the processor address strobe
signal. When asserted,
it
indicates that the address
lines
(A1 to A1
9)
are valid.
Active low. When this signal is asserted along with
AS*, the processor uses
A1
to
A8
to access one of the
device registers or put a value on the
RGA
outputs to
select registers outside the device.
Active low. When this signal is asserted together with
AS*, the processor is doing a DRAM access. The pro-
cessor supplies an address on the
At to A18 inputs
and the device multiplexes this address onto the
MA
outputs; during the same cycle, the processor con-
trols the A1
9
line to select one of the RAS lines.
This signal defines the data bus transfer as a read or
write cycle to memory. The signal is only enabled
when the processor is undergoing a
DRAM
access.
A
low on this signal signifies a processor write cycle to
memory; a high indicates
a
processor read cycle from
memory.
The device controls this signal to indicate either a
DMA
or processor
DRAM
readlwrite access. In both
cases, a low on this line indicates a write operation
and a high indicates a read operation.
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