INTERFACE SIGNALS
02-Clock Input
The 02 clock is a
TT1
compatible input used for internal device oper-
ation and as a timing reference for communicating with the system
data bus.
CS-Chip Select Input
The CS input controls the activity of the 8520. A low level on CS
while 02 is high causes the device to respond to signals on the
R/W
and address (RS) lines. A high on CS prevents these lines from con-
trolling the 8520. The CS line is normally activated (low) at 02 by
the appropriate address combination.
M-Reamrite Input
The
FUW
signal is normally supplied by the microprocessor and con-
trols the direction of data transfers of the 8520.
A
high on
R/W
indi-
cates a read (data transfer out of the 8520). while a low indicates a
write (data transfer into the 8520).
RS3-RSO
-
Address
The address inputs select the internal registers as described by the
Inputs
Register Map.
DB7-DBO
-
Bus
The eight bit data bus transfers information between the 8520 and
Inputs/o~tputs
the system data bus. These pins are high impedance inputs unless CS
is low and
FUW
and 02 are high, to read the device. During this read,
the data bus output buffers are enabled, driving the data from the
selected register onto the system data bus.
1RQ-Intempt Request
IRQ is an open drain output normally connected to the processor in-
output
terrupt input. An external pullup resistor holds the signal high, allow-
ing multiple IRQ-outputs to be connected together. The IRQ output
is normally off (high impedance) and is activated low as indicated in
the functional description.
RES-Reset Input
A
low on the RES pin resets all internal registers. The port pins are
set as inputs and port registers to zero (although a read of the ports
will return all highs because of passive pullups). The timer control
registers are set to zero and the timer latches to all ones. All other
registers are reset to zero.
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