Buffer Control Logic
The buffer control logic controls output enable and direction of the
bidirectional tri-state bus drivers. See the STEERING PAL equation.
Table 3-2.
Data Driver Timing
It
should be noted that the backplane drivers must not turn on until
the rise of
S4
during a read. This
is
okay because data from the
Amiga internal
RAMS
is
not valid during S4 anyway, so nothing is to
be gained by turning the data buffers on earlier.
Clock Buffers,
7M,
and
There are three clocks coming from the Amiga. These are CDAC,
ASDELAYED*
C1
*,
and C3*. The backplane must generate 7M (equivalent to the
Processor clock) by the following equation:
7M
=
C1
*
XNOR C3*.
THE
PRUI"I'COLS
The bus protocols are basically the same as standard
68000
proto-
cols; however, the timing margins are tighter due to the potentially
long paths of Amiga and
PlCs talking to each other across two buf-
fered backplanes.
One unusual feature is that when you are doing a DMA transfer into
or out of the Amiga display RAM (the half megabyte starting at
address
000000), the DTACK* circuit will synch the master up with
Cl. Because C1 is twice as slow as 7M, there are two possible phase
relationships between C1 and the beginning of the DMA bus cycle. If
AS* is asserted during the last quartile of C1 (C1 low and C3 low, see
Fig. 3.2, System clock timing diagram), we call this an "in sync" bus
cycle, and DTACK* is given in time to do a normal 4-clock (7M) bus
cycle. (Note: Occasionally, DTACK* is delayed due to contention with
the graphics chips, but that does not matter in this discussion.)
However, DTACK works differently if the DMA controller asserts
AS* in the other phase. In the second quartile (C1 high and C3 high),
the DTACK* circuit holds off DTACK* long enough to insert one wait
state, thus synching up the "out of sync" bus cycle.
Read or Write Cycle
Since the Amiga bus master
is
a
68000,
the bus cycle
is
a
68000
With
Amiga as Master
cycle. However, the responding slave does not pull DTACK*. Our in-
ternal circuitry pulls DTACK* unless the slave pulls XRDY low.
Also, the slave (PIC) must pull
its
SLAVE* output low as soon as
it
is
selected, and at the end of the cycle, disassert SLAVE* when AS*
goes away.
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