Read or Write Cycle
A
PIC as master must drive the bus using the same protocol as the
with
a
PIG
as
Master
68000. Some of the timing margins must be better than those from
the
68000,
because the PIC is driving through several levels of buff-
ers, and the Amiga logic
is
designed to the
68000
(8
megahertz
part) specs. Specific timing requirements can be found in the tables
later in
this
section.
Bus Arbitration
The bus arbitration scheme is based on the
68000
BR*,BG*,BGACK*
protocol. PlCs are required to assert BR* clocked by the rising edge
of
7M.
This makes
it
less expensive to design bus arbitration logic
that will be reliable. Specifically, synchronous arbitration logic can be
clocked on
7M
without danger of going metastable.
SYSTEM LEVEL
ORGANIZATION (AND
Address Override (OVR*)
Pin
17
OVR* can only be used in between address
$200000
and
A0000, and implies you have to supply your own DTACK*. OVR*
is
not
supported for the purpose of disabling system decoding in the
COO000 to DFFFFF range. Worst case
68000
timing requires modi-
fications to the system decode gate array to accomplish
this
reliably.
Other uses of OVR* are not supported.
INTERRUPTS
USE
IN7"2+
OR
INm* (DON'T
There are
two
interrupt input lines on the
PULL IPLO*-IPL2*)
Amiga: INTZ* and INT6*. INTZ*
=
pin
19.
INT6*
=
in
22.
these lines assert
levels 2 and
6'to the processor
Do
not assert the IPLO* thru IPE* lines,
because they are already driven by
internal logic.
To Next Page
Loading...
