EXAMPLE
BACKPLANE
We have designed a backplane as an example implementation of our
DESIGN
expansion architecture. This section is a detailed description of the
schematic of that backplane. The schematic appears as Figure A-l in
Appendix A.
Backplane Schematic
While reading this section, refer to the backplane schematics for the
ove~ew
A2000 and PALS to see what is being described. The B2000 uses a
gate array to handle steering; however,
this
example backplane de-
sign
is
functionally equivalent, and should be useful in that sense.
The bus comes in on the left from the processor via
J10. Note that
both the data bus and address bus are buffered through
bi-direction-
al buffers. The buffers are bi-directional in order to allow external
DMA controllers.
The
BUS
Buffers and
This subsection describes the bus buffers, their timing and control
Their
C0ntr0l
Logic
logic. In this discussion, "upstream" means away from the processor,
and "downstream" means toward the processor. For instance, if you
daisy chain two devices on the bus, the further away of the two
is
"upstream" from the closer (downstream) device.
Throughout this document, there are references to signals going ac-
tive. Active is defined in the glossary for this section.
The Address and
Control Buffers
The address lines, function codes, UDS*. LDS*,
W,
and AS* are all
buffered in the same manner by
74F245s. Their buffer direction is
determined by DMAOUT. They are enabled by
ADDROE* (address
output enable bar).
Generating
DMAOUT
This section explains the PAL equation for DMAOUT found in the
STEERING PAL equations. (Table 3-2, later in this section).
DMAOUT active means that the current bus master
is
upstream of
the buffers. Since the buffers are at the extreme downstream end of
this backplane, the master is either on this backplane or upstream
from this backplane. Thus when DMAOUT
is
high, the drivers drive
the address and control lines downstream (toward the Amiga).
The PAL equation for DMAOUT is very straightforward:
DMAOUT
=
DMAlN
+
OWN
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