DMAlN
is
active when the bus master is upstream from this back-
plane. So when
DMAlN
is active, DMAOUT must go active.
OWN* is the wire
OR'ed signal which means that this backplane has
the current bus master. Thus, because all
PlCs on this backplane are
upstream from the address (and data) buffers, DMAOUT must be
active when OWN (or OWN*) is active.
Generating ADDROE*
This section explains the PAL equation for ADDROE*. Refer to the
STEERING PAL equation to see the equation (AOE).
ADDROE* is active (enabling the address drivers) most of the time.
It
only disables the drivers when ownership of the bus is changing
(for example, a new master takes control). At these transition times,
ADDROE* is inactive so that the tri-state drivers will not fight the
drivers on the next backplane while they are changing direction.
Refer to the equation for AOE in the STEERING PAL equation (Table
3-2).
AOE
=
ADDROE* inverted. The inverter is in the output stage
of the PAL.
BGACK is asserted (BGACK* pulled low) by all bus masters (except
the
68000)
when they are the current master, so ADDROE*
is
active when BGACK is active.
The term (BG*
*
DMAOUT*) is true most of the time that the
68000
owns the bus. However, when the
68000
is
about to give up the bus,
BG* will go active and thus (BG*
*
DMAOUT*) will go inactive.
It
is
,
important that the address drivers remain on until the end of the
fi-
nal
68000
bus cycle when the
68000
is giving up the bus, so the
term AS holds AOE active when
BG
goes active during the bus cycle.
AS does not last quite long enough, so
ASQ9O (which
is
a slightly de-
layed AS) holds AOE active long enough to finish the cycle.
The Data Buffers
This section describes when and why the data drivers are turned on
and off.
It
also describes control of data direction.
Generating
DBOE*
Refer to the STEERING PAL equation for DBOE.
Note that all the bus drivers are enabled for every bus cycle unless
BERR* is asserted. This allows for easier use of bus-monitoring tools
such as state analyzers.
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