7MHZ
Clock
ADDRESSING
AND
CONTROL SIGNALS
This is the 7.1
6
MHz system clock. On A2000/B2000 design has
true
7MHz which is actually in common with the
68000's
7MHz in-
put. On the original ZORRO bus specification this was the
EQU7MHz
signal, a 7M equivalent made using the relationship EQU7MHz
=
/C1
XNOR
/C3.
Because of this, there may be some timing differ-
ences in this signal among different vendors of ZORRO expansion
boards and between these ZORRO boards and the
A2000/B2000
system.
It
is possible to create an EQU7MHz clock on a ZORRO
board that is nearly identical to the internal version, as on an A2000
the signal
is
created using exactly this aforementioned relationship.
Pin 92.
These signals are various items used for the addressing of devices on
the bus by the
68000
and any DMA devices. Most of these signals
are
bufiered versions of similar
68000
signals, and are bidirectional-
ly buffered to allow any DMA device on the bus to drive the
68000
local bus when such a device is a bus master.
Read Enable (READ)
Read enable for the bus, which is a buffered version of the 68000's
R/W
output. Read asserted indicates a read or internal cycle, read ne-
gated indicates a write cycle. Pin 68.
Address Bus (AI
-A23)
This is a buffered version of the
68000's
address bus, providing 16
megabytes of address space, though only
8
megabytes of this ad-
dress space
is
available to expansion bus devices. Expansion boards
should only respond to address ranges assigned them during con-
figuration; otherwise, addressing conflicts between multiple boards
will arise. See Appendix for pin list.
Address Strobe (/AS)
The falling edge of this strobe indicates that addresses are valid, the
rising edge signals the end of an Expansion Bus memory cycle. This
is
a buffered version of the
68000
/AS signal. Found on pin 74.
Data
Bus (DO-D
1
S)
This
is
a buffered version of the
68000's
data bus, providing 16 bits
of data accessible by word or either byte. Note that the data bus
is
enabled by /AS asserted, so the data bus
is
not expected to have any
significant hold time beyond
/AS negated, so during write cycles in
most design applications /AS should not be used to latch data. During
read cycles, the enabling of the data bus
is
delayed to give the colli-
sion detection circuitry time to detect any collisions before data
is
en-
abled, thus avoiding any fights among the data drivers of multiple
PICs. See Appendix for pin list.
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