Data Strobes (/LDS,
NDS)
These are buffered versions of the 68000's upper and lower data
strobes. The strobes fall on data valid during transfer; the lower
strobe being used for the lower byte (even byte address), the upper
strobe being used for the upper byte (odd byte address). These are
considered by the data bus buffers during read cycles, in case the cy-
cle actually turns out to be a read-modify-write cycle. They're ig-
nored during write cycles, since they can become valid quite late in
the cycle, and a late enable would require unnecessarily fast data
handling in certain PIC applications. Pins:
70,
72.
Valid Memory Address
Unbuffered output from the
68000
indicating a valid address for
(NMA)
6800
style peripheral devices. in response to a NPA input. Pin 51.
Valid Peripheral Address
Unbuffered input to the
68000
indicating the address has selected a
(NPA)
6800
or 6502 style peripheral, so the
6800
style peripheral access
should take place. Pin 48.
Data Transfer
This signal is logically associated with the
68000's
Data Transfer Ac-
Acknowledge (IDTACK)
knowledge input. Normally in the Amiga system. Amiga system logic
creates
IDTACK for a simple, no-wait state cycle (this may be varied
by the custom chips). Therefore, this signal
is
treated as an output to
the Expansion and Coprocessor Slots, for most situations. Any slow
device on the bus that needs to control
IDTACK may do so by negat-
ing XRDY to hold off
IDTACK or asserting /OVR very quickly to tri-
state IDTACK. Note that depending upon when /AS
is
asserted by a
bus master when accessing the
CHIP memory, one of two possible
cycles may result. If /AS is asserted during C1 low, C3 low, the bus
cycle is considered "in-sync," and will proceed, with
IDTACK driven
as for a normal,
4
tick clock cycle. If, instead. /AS is asserted during
C1 high. C3 high, the bus cycle
is
considered "out of sync" and the
internally generated
IDTACK will be held off, causing a wait state
that's designed to "sync-up" the DMA cycle with the custom chip's
memory cycle. This signal is on pin 66.
Processor Status
(FCO-FC2)
These signals are the buffered versions of the
68000
Processor Sta-
tus outputs, which can be used by bus devices to determine the inter-
nal state of the
68000
any time /AS is asserted. Pins 31.33.35.
To Next Page
Loading...
