Bus Error (BERR)
This is an input that goes directly to the 68000.
It
is used
to
indicate
the occurrence of some kind of bus error. Any expansion card capa-
ble of detecting a bus error relating directly to that card can assert
IBERR when that bus error condition
is
detected. At other times, the
card must monitor
IBERR and be prepared to tri-state all of
its
on-
bus output buffers whenever this signal
is
asserted. Since any num-
ber of devices may assert
IBERR, and all bus cards must monitor
it,
any device that drives IBERR must drive with an open collector or
similar device capable of sinking at least 1
Zma, and any device that
monitors
IBERR should place as little load on
it
as possible (1
"F"
type load or less, per board, is suggested). This signal
is
connected to
a low valued on-board
pullup resistor, and shouldn't need any more
pulling up. Pin 46.
System
Reset
(/RST,
Pin
53
of the bus contains the IRST signal, pin
94
contains the
/BUSRST)
IBUSRST signal. Both of these reflect system reset, however, the
IRST signal
is
bidirectional, unbuffered, and in common with the
original
68000
reset signal.
It
should only be used on boards that are
capable of resetting the system. The
IBUSRST signal
is
a buffered
output-only version of the reset signal that should be used as the
normal reset input to boards not concerned with resetting the sys-
tem on their own. The
IRST signal
is
connected to a medium valued
on-board
pullup resistor and shouldn't need any more pulling up.
System Halt (MLT)
System Interrupts
This is the 68000's processor halt signal, tied directly to the 68000.
It
is connected to a medium valued on-board pullup resistor and
shouldn't need any more pulling up. This signal, when driven by
a
Plc, will halt and tri-state the
68000
at the end of the current bus
cycle. If driven by the
68000,
it
indicates detection of a double bus
fault. Pin
55.
Six of the
68000
interrupts are available on the Expansion Bus, and
these are labelled as
/INT2,/INT6, IEINTl, lEINT4, IEINTS, lEINT7.
The interrupt structure of the original ZORRO specification has been
slightly changed for the
A2000lB2000. This change affects the avail-
ability of decoded interrupt inputs and multiplexed interrupt inputs.
Specifically, the
68000
accepts
7
levels of interrupt that are present-
ed to
it
as
8
possible values priority encoded into
3
multiplexed in-
puts. The original ZORRO specification called for decoded interrupt
inputs on pin 19 for interrupt level
2
(IINTZ), and on pin 22 for in-
terrupt level
6
(lINT6). These are the same interrupts used by the
Amiga internal system chips and encoded by the Paula chip. The in-
terrupts could be used by external devices by wired
ORing interrupt
requests into one of these available interrupts. The original ZORRO
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