PIC
is
DMA Owner
(/OWN)
Asserted by Expansion Bus
DMA
device when
it
becomes bus master.
This output is to be treated as a wired-OR output between all Expan-
sion Slots, any of which may have a PIC signalling bus mastership.
Thus, this should be driven with an open-collector or similar output
by any PIC using it. Found on pin
7.
Slot S~ecific BUS
Pins 60 and
64
are, respectively, the IBRn and IBGn signals, where
hbitr&ion
(BR~
/BGn)
"n"
refers to the Expansion slot number. Each Slot has
its
own ver-
slon of each sianal. The Bus Request and Bus Grant from each board
go to some
prkritization circuih, and then to the 68000. Slot
1
has
the highest priority, Slot
5
the lowest, out of the Expansion Slots. On
a
B2000, the Coprocessor Slot is included in this priority chain when
its not acting as a coprocessor, and
it
acts as priority level
0,
right be-
fore that of slot
1.
Note that along with the request prioritization
logic, the bus requests are clocked by the rising edge of the
7M
clock,
and its a very good idea for any PIC requesting the bus to similarly
clock its Bus Request output. This design prohibits any astable or
race conditions that can occur when two
PlCs desire to own the bus
asynchronously. Found on pins 60,
64,
respectively.
Bus Grant Acknowledge
This is the unbuffered 68000 IBGACK signal. Any PIC that receives a
(/BWCK)
bus grant from the 68000 should assert this signal as long as the
DMA
continues, releasing
it
once the DMA request is finished. This
signal should never be asserted until the Bus Grant has been re-
ceived, AS is negated, DTACK is negated, and BGACK itself is negat-
ed, indicating that all other potential bus masters have relinquished
the bus. This output is driven as a wired-OR output, so all devices
driving
it
must drive
it
with an open collector or equivalent device.
Pin
62.
Processor
BUS Grant
The A1
000
and A2000 systems receive the the /BG (bus grant) sig-
(BG,
IGBG)
nal from the
68000
directly, unchanged, in addition to the slot spe-
cific /BGn signals. This was actually a late change to the original
ZORRO specification, so
it
may not
be
on every
A1
000
ZORRO ex-
pansion box. This has changed slightly on the B2000 system as part
of the coprocessor interface. The
B2000's bus pin
95
is /G&, Ge-
neric Bus Grant. When the
68000
is
in charge, /G&
is
essentially a
buffered
/BG. When the coprocessor is in charge. IGBG
is
a buffered
ICBG. This allows all cards in the expansion bus
to
function without
concern as to which processor
is
actually controlling the bus.
RESERVED PINS
Pins
96.97.
and
98
have been left open for future expansion.
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