Data Strobes (/LDS,
IUDS)
These are the
68000's
upper and lower data strobes. The strobes
fall on data valid during transfer; the lower strobe being used for the
lower byte (even byte address), the upper strobe being used for the
upper byte (odd byte address). Like /AS, these must be driven by the
Coprocessor as
it
assumes control, as the
68000
pins will tri-state.
Pins:
70,
72.
Valid Memory Address
Output from the
68000
indicating a valid address for
6800
style pe-
(NMA)
ripheral devices, in response to a IVPA input. This output goes tri-
state when the Coprocessor takes over from the
68000,
and as such
must be re-created by the coprocessor in response to a VPA signal
from somewhere on the motherboard. Pin 51.
Valid Peripheral Address
Input to the
68000
indicating the address has selected a
6800
or
(NW
6502 style peripheral, so the
6800
style peripheral access should
take place. When the
68000
has given up the bus to the Coproces-
sor, this input is ignored and must be handled by the Coprocessor
board. Pin
48.
Data Transfer
This signal
is
the 68000's Data Transfer Acknowledge input, though
Acknowledge (IDTACK)
it's being driven on the motherboard under most conditions. Nor-
mally in the Amiga system, Amiga system logic creates
IDTACK for a
simple, no-wait state cycle (this may be varied by the custom chips).
Therefore, this signal
is
treated as an output to the Expansion and
Coprocessor Slots, for most situations. Any slow device on the bus
that needs to control
IDTACK may do so by negating XRDY to hold
off
IDTACK or asserting /OVR very quickly to tri-state IDTACK. Any
coprocessor must be able to support this action by Expansion boards
as well. Note that depending upon when /AS is asserted by a bus
master when accessing the
CHIP memory, one of two possible cycles
may result. If /AS is asserted during C1 low, C3 low, the bus cycle
is
considered "in-sync," and will proceed, with IDTACK driven as for a
normal
4
tick clock cycle. If instead, /AS is asserted during C1 high,
C3 high, the bus cycle is considered "out of
sync" and the internally
generated
IDTACK will be held off, causing a wait state that's de-
signed to "sync-up" the DMA cycle with the custom chip's memory
cycle. Of course, when a coprocessor is accessing any of
its
on-board
resources, the designer can implement any reasonable data transfer
scheme that comes to mind. This signal
is
on pin 66.
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