Compaq Deskpro 4000N - Page 6

Technical Reference Guide
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
iv
CHAPTER 4 SYSTEM SUPPORT.........................................................................................................
4.1 INTRODUCTION.................................................................................................................. 4-1
4.2 PCI BUS OVERVIEW........................................................................................................... 4-2
4.2.1 PCI CONNECTOR.........................................................................................................4-3
4.2.2 PCI BUS MASTER ARBITRATION.............................................................................. 4-4
4.2.3 PCI BUS TRANSACTIONS........................................................................................... 4-5
4.2.4 OPTION ROM MAPPING .............................................................................................4-8
4.2.5 PCI INTERRUPT MAPPING......................................................................................... 4-9
4.2.6 PCI CONFIGURATION............................................................................................... 4-10
4.3 ISA BUS OVERVIEW......................................................................................................... 4-11
4.3.1 ISA CONNECTOR ......................................................................................................4-12
4.3.2 ISA BUS TRANSACTIONS......................................................................................... 4-13
4.3.3 DIRECT MEMORY ACCESS...................................................................................... 4-15
4.3.4 INTERRUPTS.............................................................................................................. 4-18
4.3.5 INTERVAL TIMER..................................................................................................... 4-22
4.3.6 ISA CONFIGURATION............................................................................................... 4-22
4.4 SYSTEM CLOCK DISTRIBUTION.................................................................................... 4-23
4.5 REAL-TIME CLOCK AND CONFIGURATION MEMORY............................................... 4-24
4.5.1 CONFIGURATION MEMORY BYTE DEFINITIONS ................................................ 4-25
4.6 I/O MAP AND REGISTER ACCESSING............................................................................ 4-41
4.6.1 SYSTEM I/O MAP ...................................................................................................... 4-41
4.6.2 87307 I/O CONTROLLER CONFIGURATION ........................................................... 4-42
4.7 SYSTEM MANAGEMENT SUPPORT ............................................................................... 4-44
4.7.1 FLASH ROM WRITE PROTECT ................................................................................4-44
4.7.2 PASSWORD PROTECTION........................................................................................ 4-45
4.7.3 I/O SECURITY............................................................................................................ 4-46
4.7.4 USER SECURITY........................................................................................................ 4-46
4.7.5 TEMPERATURE SENSING........................................................................................4-47
4.7.6 POWER MANAGEMENT........................................................................................... 4-48
CHAPTER 5 INPUT/OUTPUT INTERFACES.....................................................................................
5.1 INTRODUCTION.................................................................................................................. 5-1
5.2 ENHANCED IDE INTERFACE............................................................................................ 5-1
5.2.1 IDE PROGRAMMING................................................................................................... 5-1
5.2.2 IDE CONNECTORS......................................................................................................5-8
5.3 DISKETTE DRIVE INTERFACE........................................................................................5-10
5.3.1 DISKETTE DRIVE PROGRAMMING ........................................................................ 5-11
5.3.2 DISKETTE DRIVE CONNECTOR.............................................................................. 5-14
5.4 SERIAL INTERFACES.......................................................................................................5-15
5.4.1 RS-232 INTERFACE ................................................................................................... 5-15
5.4.2 SERIAL INTERFACE PROGRAMMING.................................................................... 5-16
5.5 PARALLEL INTERFACE ................................................................................................... 5-21
5.5.1 STANDARD PARALLEL PORT MODE ..................................................................... 5-21
5.5.2 ENHANCED PARALLEL PORT MODE..................................................................... 5-22
5.5.3 EXTENDED CAPABILITIES PORT MODE............................................................... 5-22
5.5.4 PARALLEL INTERFACE PROGRAMMING.............................................................. 5-23
5.5.5 PARALLEL INTERFACE CONNECTOR ................................................................... 5-27