Compaq Deskpro 4000N - Table of Contents

Technical Reference Guide
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
iii
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION.............................................................................................................
1.1 ABOUT THIS GUIDE ........................................................................................................... 1-1
1.1.1 USING THIS GUIDE.....................................................................................................1-1
1.1.2 ADDITIONAL INFORMATION SOURCES.................................................................. 1-1
1.2 NOTATIONAL CONVENTIONS.......................................................................................... 1-2
1.2.1 VALUES........................................................................................................................ 1-2
1.2.2 RANGES........................................................................................................................ 1-2
1.2.3 SIGNAL LABELS..........................................................................................................1-2
1.2.4 REGISTER NOTATION AND USAGE ......................................................................... 1-2
1.2.5 BIT NOTATION............................................................................................................1-2
1.3 COMMON ACRONYMS AND ABBREVIATIONS..............................................................1-3
CHAPTER 2 SYSTEM OVERVIEW.....................................................................................................
2.1 INTRODUCTION.................................................................................................................. 2-1
2.2 FEATURES........................................................................................................................... 2-2
2.2.1 STANDARD FEATURES.............................................................................................. 2-2
2.2.2 MODEL DIFFERENCES ............................................................................................... 2-3
2.2.3 OPTIONS.......................................................................................................................2-3
2.3 MECHANICAL DESIGN...................................................................................................... 2-4
2.3.1 CABINET LAYOUT...................................................................................................... 2-4
2.3.2 CHASSIS LAYOUT....................................................................................................... 2-6
2.3.3 SYSTEM BOARD LAYOUT ......................................................................................... 2-7
2.4 SYSTEM ARCHITECTURE..................................................................................................2-8
2.4.1 MICROPROCESSOR................................................................................................... 2-10
2.4.2 MEMORY.................................................................................................................... 2-10
2.4.3 SUPPORT CHIPSET....................................................................................................2-11
2.4.4 MASS STORAGE........................................................................................................ 2-11
2.4.5 SERIAL AND PARALLEL INTERFACES .................................................................. 2-11
2.4.6 UNIVERSAL SERIAL BUS INTERFACE................................................................... 2-12
2.4.7 GRAPHICS SUBSYSTEM........................................................................................... 2-12
2.5 SPECIFICATIONS.............................................................................................................. 2-13
CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM........................................................................
3.1 INTRODUCTION.................................................................................................................. 3-1
3.2 PENTIUM MMX-BASED PROCESSOR/MEMORY SUBSYSTEM..................................... 3-2
3.2.1 PENTIUM MMX MICROPROCESSOR......................................................................... 3-3
3.2.2 BUS/PROCESSING SPEED SELECT............................................................................ 3-4
3.2.3 SECONDARY (L2) CACHE MEMORY........................................................................3-4
3.2.4 SYSTEM MEMORY...................................................................................................... 3-5
3.2.5 SUBSYSTEM CONFIGURATION................................................................................. 3-8