Cypress Semiconductor CY7C68013A - Page 45

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 45 of 62
10.9 Slave FIFO Synchronous Write
Figure 20. Slave FIFO Synchronous Write Timing Diagram
[20]
Z
Z
t
SFD
t
FDH
DATA
IFCLK
SLWR
FLAGS
t
WRH
t
XFLG
t
IFCLK
t
SWR
N
Table 23. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
[21]
Parameter Description Min Max Unit
t
IFCLK
IFCLK Period 20.83 ns
t
SWR
SLWR to Clock Setup Time 10.4 ns
t
WRH
Clock to SLWR Hold Time 0 ns
t
SFD
FIFO Data to Clock Setup Time 9.2 ns
t
FDH
Clock to FIFO Data Hold Time 0 ns
t
XFLG
Clock to FLAGS Output Propagation Time 9.5 ns
Table 24. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK
[21]
Parameter Description Min Max Unit
t
IFCLK
IFCLK Period 20.83 200 ns
t
SWR
SLWR to Clock Setup Time 12.1 ns
t
WRH
Clock to SLWR Hold Time 3.6 ns
t
SFD
FIFO Data to Clock Setup Time 3.2 ns
t
FDH
Clock to FIFO Data Hold Time 4.5 ns
t
XFLG
Clock to FLAGS Output Propagation Time 13.5 ns
[+] Feedback [+] Feedback