Dell EMC PowerEdge R340 - Initial System Setup and Configuration; Setting Up Your System; iDRAC Configuration

Feature Description
GPIOs than the ones provided by the PCH. The solution requires
external shift register discrete components
System Management Bus (SMBus 2.0) The chipset provides a System Management Bus (SMBus) 2.0
host controller as well as an SMBus Slave Interface. The chipset
is also capable of operating in a mode in which it can
communicate with I2C compatible devices. The host SMBus
controller supports up to 100-KHz clock speed.
JTAG Boundary-Scan This section contains information regarding the chipset
testability signals that provides access to JTAG, run control,
system control, and observation resources. PCH JTAG (TAP)
ports are compatible with the IEEE Standard Test Access Port
and Boundary Scan Architecture 1149.1 and 1149.6 Specication,
as detailed per device in each BSDL le. JTAG Pin denitions are
from IEEE Standard Test Access Port and Boundary-Scan.
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