Denon AVC-4310 - IC Pin Assignments and Functions (Continued); R5 F3650 TNFB;KNFB Terminal Functions (Continued)

85
AVR-4310CI/AVR-4310/AVC-4310
73 P15/INT3 ADVINT3 I-
E ↓& L
- - Z - - Z
HDMI RECEIVER(ADV7840)INT3 output
74 P14 (DSP3 ICS)/SUBD
CLK
OC - - - Z O/L O/L Z
Not used
75 P13/TXD6 DSP MOSI OC - - - Z O/L O/L Z
DSP cotrol pin (ADSP-21367-333)
76 P12/RXD6 DSP MISO I- Lv - - Z - - Z
DSP cotrol pin (ADSP-21367-333)
77 P11/CLK6 DSPICLK OC - - - Z O/L O/L Z
DSP cotrol pin (ADSP-21367-333
78 P10 Z1VSIG.DET I- Lv - - Z - - Z
VIDEO IN signal detect input (Detected : H)
79 P07 PLD WRITE OC - - - Z O/L O/L Z
PLD JTAGLINE ON/OFF control
80 P06 VSEL C1 OC - - - Z O/L
MODE1=O/H
MODE2=O/L
Z
GUI built-in VIDEO SW cotrol pin /PLDrewrite
control (JTAG)
81 P05 HPD3 OC - - - Z O/L - Z
HD DET cotrol pin
82 P04 HPD4 OC - - - Z O/L - Z
HD DET cotrol pin
83 P03 HPD5 OC - - - Z O/L - Z
HD DET cotrol pin
84 P02 DIR RST3 I- Lv - - Z - - Z
DIR cotrol pin (LC89058W-VF4A)
85 P01 DIR RST2 OC - - - Z O/L O/L O/L
DIR cotrol pin (LC89058W-VF4A)
86 P00 DIR RST1 OC - - - Z O/L O/L O/L
DIR cotrol pin (LC89058W-VF4A)
87 P107/(AN7) DSP2 RST OC - - - Z O/L O/L Z
DSP2(ADSP-21367-333) reset output pin(Reset:
L)
88 P106/(AN6) DSP1 RST/
SubnCONFIG
OC - - - Z O/L O/L Z
DSP1(ADSP-21367-333) reset output pin(Reset:
L)/FPGA rewrite (MAIN FPGA
＆ GUI
FPGAcombined use)
89 P105/(AN5) DSP ROMRST/
SUBnCE
OC - - - Z O/L O/L Z
DSP memory reset(reset: L/FPGA rewrite control
(MAIN FPGA ＆ GUI FPGAcombined use)
90 P104/(AN4) COMPS DET I- Lv -
SCPU3VPu
Z - - Z
COMPONENT IN signal detect input
91 P103/(AN3) DSP2 FLAG0/
SUBDATA_0
I/O - Lv -
Pd
Z - - Z
DSP2 cotrol pin (ADSP-21367-333)/FPGA
rewrite control (MAIN FPGA ＆ GUI
FPGAcombined use)
92 P102/(AN2) DSP2 ICS/
SUBnCS
OC -
D3VPu
Z O/L O/L Z
DSP2 cotrol pin (ADSP-21367-333)/FPGA
rewrite control (MAIN FPGA ＆ GUI
FPGAcombined use)
93 P101/(AN1) DSP1 ICS/
SUBASDI
OC -
D3VPu
Z O/L O/L Z
DSP1 cotrol pin (ADSP-21367-333)/FPGA
rewrite control (MAIN FPGA ＆ GUI
FPGAcombined use)
94 AVSS AVSS -- - - - - - - -
AD GND
95 P100/(AN0) VSEL CLK OC - - - Z O/L O/L Z
GUI built-in VIDEO SW cotrol pin
96 VREF VREF -- - - - - - - -
AD ref. +3.3V
97 AVCC AVCC -- - - - - - - -
AD +3.3V
98 P97/(SIN4) Tx EN OC - - - Z O/L - Z
AD8195 ENABLE pin for Front HDMI cotrol
99 P96/(SOUT4) DSP1 FLAG0/
SUBCONF_DONE
I- - -
Pd
Z O/L O/L Z
DSP1 cotrol pin (ADSP-21367-333)/FPGA
rewrite control (MAIN FPGA ＆ GUI
FPGAcombined use)
100 P95/(CLK4) VEXP DIN OC - - - Z O/L O/L Z
VIDEO expander control DATA output
(BU4094BCFV)
Pin Pin Name Symbol I/O Type Det
Op
(Int.)
Pu/Pd
(Ext.)
Res PURE D
CEC
STBY
P. OF F Function