Denon AVR-S750H Service Manual

DIGITAL_OSD : IC732
BY25Q32BSSIG (except : E2)
BY25Q64ASSIG (only E2)
SN74CBT3251PWR (DIGITAL_OSD : IC733)
Block diagram
1
2
3
4
8
7
6
5
Top View
SOP8 208mil
/CS
SO
/WP
VSS
VCC
/HOLD
SCLK
SI
Pin Name
I/O
Description
/CS I Chip Select
SO (IO1) I/O
Serial Output for single bit data Instructions. IO1 for Dual or Quad
Instructions.
/WP (IO2) I/O
Write Protect in single bit or Dual data Instructions. IO2 in Quad mode.
The signal has an internal pull-up resistor and may be left unconnected
in the host system if not used for Quad Instructions.
VSS Ground
SI (IO0) I/O
Serial Input for single bit data Instructions. IO0 for Dual or Quad
Instructions.
SCLK
I
Serial Clock
/HOLD (IO3) I/O
Hold (pause) serial transfer in single bit or Dual data Instructions. IO3 in
Quad-I/O mode. The signal has an internal pull-up resistor and may be
left unconnected in the host system if not used for Quad Instructions.
VCC Core and I/O Power Supply
SN74CBT3251
1-OF-8 FET MULTIPLEXER/DEMULTIPLEXER
SCDS019L − MAY 1995 − REVISED JANUARY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
 5-Ω Switch Connection Between Two Ports  TTL-Compatible Input Levels
1 2 3 4 5 6 7 8
16 15 14 13 12
11
10
9
B4 B3 B2 B1
A
NC OE
GND
V
CC
B5 B6 B7 B8 S0 S1 S2
D, DB, DBQ, OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
RGY PACKAGE
(TOP VIEW)
1 16
89
2 3 4 5 6 7
15 14 13 12 11 10
B5 B6 B7 B8 S0 S1
B3 B2 B1
A
NC OE
B4
S2
V
GND
CC
NC − No internal connection
description/ordering information
The SN74CBT3251 is a 1-of-8 high-speed TTL-compatible FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. When output enable (OE
) is low, the SN74CBT3251 is enabled. S0, S1, and S2 select one of the B outputs for
the A-input data.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Tape and reel SN74CBT3251RGYR CU251
SOIC D
Tube SN74CBT3251D
CBT3251
SOIC − D
Tape and reel SN74CBT3251DR
CBT3251
−40°C to 85°C
SSOP − DB Tape and reel SN74CBT3251DBR CU251
40 C
to
85 C
SSOP (QSOP) − DBQ Tape and reel SN74CBT3251DBQR CU251
TSSOP PW
Tube SN74CBT3251PW
CU251
TSSOP − PW
Tape and reel SN74CBT3251PWR
CU251
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Copyright © 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74CBT3251
1-OF-8 FET MULTIPLEXER/DEMULTIPLEXER
SCDS019L − MAY 1995 − REVISED JANUARY 2004
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each multiplexer/demultiplexer)
INPUTS
FUNCTION
OE S2 S1 S0
FUNCTION
L L L L A port = B1 port
L L L H A port = B2 port
L L H L A port = B3 port
L L H H A port = B4 port
L H L L A port = B5 port
L H L H A port = B6 port
L H H L A port = B7 port
L H H H A port = B8 port
H X X X Disconnect
logic diagram (positive logic)
B5
B1
A
B2
B3
B4
B6
B7
B8
OE
S0
S1
S2
5
7
11
10
9
4
3
2
1
15
14
13
12
TPS563201 (DIGITAL_DIGITAL SUPPLY : IC741, IC742, IC743, IC744)
Terminal Functions
PIN
DESCRIPTION
NAME
NUMBER
(I/O)
GND 1(-)
Ground pin Source terminal of low-side power NFET as well as the ground ter-
minal for controller circuit. Connect sensitive VFB to this GND at a single point.
SW 2(O) Switch node connection between high-side NFET and low-side NFET.
VIN 3(I) Input voltage supply pin. The drain terminal of high-side power NFET.
VFB 4(I)
Converter feedback input. Connect to output voltage with feedback resistor
divider.
EN 5(I) Enable input control. Active high and must be pulled up to enable the device.
VBST 6(O)
Supply input for the high-side NFET gate drive circuit. Connect 0.1 μ F capaci-
tor between VBST and SW pins.
Block diagram
GND 1 VBST
6
SW 2 EN5
VIN 3 VFB4
DDC Package
6-Pin SOT
Top View
2 SW
ZC
PWM
Control Logic
+
+
+
UVP
OVP
3 VIN
t
ON
One-Shot
6 VBST
+
4V F
B
OCL
+
+
Soft Start
5E N
HS
LS
1 GND
SS
Voltage
Reference
Ref
Hiccup
V
UVP
OCL
Threshold
Regulator
UVLO
VREG5
VREG5
TSD
V
OVP





XCON
Before Servicing
This Unit
Electrical Mechanical Repair Information Updating
49

Denon AVR-S750H Specifications

General

Receiver type	stereo
Frequency range	10 - 100000 Hz
Input sensitivity	200 mV
Audio output channels	7.2 channels
Signal-to-Noise Ratio (SNR)	98 dB
Total Harmonic Distortion (THD)	10 %
Power output per channel (1KHz@6 Ohm)	165 W
Power output per channel (20-20KHz@8 Ohm)	75 W
AirPlay	Yes
Display	VFL
HDCP version	2.3
Apple docking	No
Product color	Black
Audio decoders	DTS-HD Master Audio, Dolby TrueHD
Volume control	Rotary
HDMI in	6
Composite video in	2
Digital audio optical in	1
Package depth	432 mm
Package width	523 mm
Package height	229 mm
Package weight	10614 g
AC input voltage	120 V
AC input frequency	60 Hz
Power consumption (standby)	0.5 W
Power consumption (typical)	400 W
AM band range	520 - 1710 kHz
FM band range	87.5 - 107.9 MHz
Supported radio bands	AM, FM
Audio formats supported	AAC, ALAC, DSD, FLAC, MP3, WAV, WMA
Image formats supported	JPEG
Speakers connectivity type	RCA

Weight and Dimensions

Depth	330 mm
Height	152 mm
Weight	8618 g