Denon DCD-1420 - CXD1125 Q Terminal Details; CXD1125 Q Terminal Function Descriptions

me
TK]
Smoot
|
vO
46
RAOY
oO
Address
output
of
external
RAM,
ADDROQ.
47
RAIO
|
0
Address
output
of
external
RAM.
ADOR10.
48
RA11
oO
peandaress
output
of
external
RAM.
ADDR11.
49
RAWE
O
Write
enable
signal
output
for
external
RAM.
(Active
at
“L’’.)
50
RACS
ie)
Chip
select
signal
output
for
external
RAM.
(Active
at
‘‘L'’.)
51
|
C4M
oO
Dividing
output
of
X’tal.
f
=
4.2336
MHz.
:
52
Vss5
-
GND
(OV).
:
53.
|
XTAI
l
X‘tal
oscillation
circuit
input.
By
selecting
of
mode,
f
=
8.4672
MHz
or
16.9344
MHz.
‘
54
XTAO
ie)
X‘tal
oscillation
circuit
output.
By
selecting
of
mode,
f
=
8.4672
MHz
or
16.9344
MHz.
e| moi
|
|
ani
Mode
eal
ce
1.
56
MD2
I
Mode
selection
input
2.
57
Tp
I
Mode selection
input
3.
58
SLOB
\
ie
ell
input
for
audio
data
output.
At
“L”
for
2’s
compliment
output;
at
“H”
for
offset
binary
59 PSSL
I
Mode switching
input
for
audio
data
output.
At
“L"’
for
serial
output;
at
““H”
for
parallel
output.
‘
60
APTR
oO
Control
output
for
aperture
compensation.
In
“H"
for
R-ch,
61
APTL
oO
Control
output
for
aperture
compensation.
In
“‘H’’
for
L-ch.
62
DAO1
O
n
Se E
ace
-
eee
aaeuee
parallel
voice
data)
output.
63
DAO2
(@)
At
PSSL =
“H"
for
DAQ2
output;
PSSL
=
“’L”
for
C1F2
output.
64
DAO3
oO ae
PSSL
=
"H"
for
DAO3
output;
PSSL
=
“’L”’
for
C2F1
output.
65
pao
|
oO
At
PSSL
=
“H”
for
DA0O4
output;
PSSL
=
‘’L”
for
C2F2
output.
66
DAOS
|
Oo
At
PSSL =
“H”
for
DAO5
output;
PSSL
=
L”
for
C2FL
output.
67
DAO6
O
At
PSSL
=
“H"
for
DAO6
output;
PSSL
=
“L”
for
C2PO
output.
68
DAO7
0
At
PSSL =
“H"”
for
DAO7
output;
PSSL
=
“L”
for
RFCK
output.
69
DAO8
Oo
At
PSSL
=
“‘H”
for
DAO8
output;
PSSL
=
““L”
for
WFCK
output.
70
DAOQ9
O
At
PSSL
=
"H"
for
DAOS
output;
PSSL
=
““L"
for
PLCK
output.
Fl
jy
DA10
re)
At
PSSL
=
‘‘H"
for
DA10
output;
PSSL
=
"’L”
for
UGFS
output.
72
DA11
ie)
At
PSSL
=
“‘H”
for
DA11
output;
PSSL
=
‘“’L”’
for
GTOP
output.
73
Voo
-
Power
supply
(+5V).
74 DA12
O
At
PSSL
=
“H”
for
DA12
output;
PSSL
=
“L”
for
RAOV
output.
75 DA13
oO
At
PSSL
=
"H"”
for
DA13
output;
PSSL
=
“‘L"
for
C4LR
output.
76
=|
DA14
fe)
At
PSSL
=
“H”
for
DA14
output;
PSSL
=
“L"
for
C210
output.
77
DA15
ce)
At
PSSL =
“H”
for
DA15
output;
PSSL
=
“’L"
for
C210
output.
78
DAI6
O
ny
ek :
ae
se
Raia
parallel
voice
data)
output.
79
WDCK
0
Strobe
signal
output.
At
DF
ON,
176.4
kHz. At
CXD1125Q
or
DF
OFF,
88.2
kHz.
80
LRCK
oO
Strobe
signal
output.
At
DF
ON,
88.2
kHz.
At
CXD1125Q
or
DF
OFF,
44.1
kHz.
pope
ree
,
:
nates
UGFS:
Output
of
unprotected
frame
sync
pattern.
Cie.
ae
output
for
error
correction
state
what
's
at
GTOP:
eee
output
of
frame
synchro
in
protected
condi-
C2F1:
Monitor
output
for
error
correction
state
what
C2
is
at
RAOV:
Overflow
and
underflow
indication
outputs
of
+4
frame
C2F2:
decode.
jitter
absorbing
RAM.
C2FL:
Correction
state
output.
Becomes
‘‘H’’
when
C2
system
C4LR:
Strobe
signal.
At
DF
ON,
352.8
kHz.
At
CXD11250
or
in
which
presently
under
correction
is
unable
to
correct.
DF
OFF,
176.4
kHz.
C2PO:
C2
pointer
indication
output.
Synchronizes
with
audio
C210:
Reverse
output
of
C210.
data
output.
;
C210:
Bit
clock
output.
At
DF
ON,
4.2336
MHz.
At
Week,
ie
Sa
aro
a
ner
esr
he
pane
on to
eet
fee
et
ra
k
aide
a
fe
DATA:
Serial
data
output
of
audio
signal.
X‘tal system.
PLCK: VCO/2 output. When locked to EFM signal, f = 4.3218
MHz.