Denon DN-D9000 - Playing the Alpha Track; Alpha Track Playback Functions; Adjusting Alpha Track Sound

12
DN-D9000
Function
I/O
Pin
No.
Pin Name
Symbol
DET Ext Ini Res
26 PC3 MUTE O — Pu H H Mute signal (H: Mute)
27 XI XI I — — — — Oscillation input
28 XO XO O — — — — Oscillation output
29 VDD VDD — — — — — Power (+3.3V)
30 OSCI OSCI I — — — — Oscillation input, 32.0MHz
31 OSCO OSCO O — — — — Oscillation output
32 VSS VSS — — — — — GND
33 BOSC 32.0MHz O — — — — System clock output
34 PC5,NMI_ RESERVE I — Pu H H
35 RST_ RST_ I — — — — µcom reset
36 PC0 LEDOUT1 O — Pu H H TRAY1 LED
37 P76 LEDOUT2 O — Pu H H TRAY2 LED
38 P60,IRQ0 JOGINT1 I — (Pu) H H JOGA pulse input for CD1 scratch
39 P61,IRQ1 JOGINT2 I — (Pu) H H JOGA pulse input for CD2 scratch
40 P62,IRQ2 DTIMA1 I — (Pu) H H CD1 main playback clock input
41 P63,IRQ3 DTIMB1 I — Pu H H CD1 monitor playback clock input
42 P64,IRQ4 ATANS_ I — Pu — H ATAPI µcom serial interface
43 P65,IRQ5 DTIMA2 I — Pu H H CD2 main playback clock input
44 P66,IRQ6 DTIMB2 I — Pu H H CD2 monitor playback clock input
45 P67,IRQ7 RESERVE O — — H —
46 P70 YMCLK O — — H — Clock for SM5902(DOUT)/PCM1608(D/A) data
47 P71 YMDATA O — — H — SM5902(DOUT)/PCM1608(D/A) output data
48 PD2,DMAACK0_ NRES_ O — Pd L L SM5902(DOUT)/PCM1608(D/A) reset signal
49 PD3,DMAREQ0_ ZSENCE1 I — — — — SM5902 µcom interface status for CD1
50 VDD VDD — — — — — Power (+3.3V)
51 P77 ZSENCE2 I — — — — SM5902 µcom interface status for CD2
52 P72 MDO I — Pd — L PCM1608(D/A) input data
53 P73 YMLD1_ O — — H — SM5902(DOUT) chip select for CD1
54 P74 YMLD2 O — — H — SM5902(DOUT) chip select for CD2
55 P75 ML O — — H — PCM1608(D/A) chip select
56 PA0,SBI0 RXD1 I — (Pu) — H Data receive from RC CD1
57 PA1,SBO0 TXD1 O — Pu H H Data send to RC CD1 (PU µcom specify)
58 PA2,SBT0 MCMD_ O — Pu H H ATAPI µcom serial interface (PU µcom specify)
59 PA3,SBI1 RXD2 I — (Pu) — H Data receive from RC CD2
60 PA4,SBO1 TXD2 O — Pu H H Data send to RC CD2
61 PA5 ATDIR O — — H — Not used
62 PB0,SBI2 X’RXD I — (Pu) — H Data receive from X’EFFECT
63 PB1,SBO2 X’TXD O — Pu H H Data send to X’EFFECT
64 PB2 APRES_ O — Pd L L ATAPI µcom reset signal (CD1, CD2 common)
65 PB3,SBI3 ATDATA I — Pu — H ATAPI µcom serial receive signal
66 PB4,SBO3 MDATA O — Pu H H ATAPI µcom serial send signal
67 PB5,SBT3 MCLK O — Pd H L ATAPI µcom serial send/receive clock
68 VDD VDD — — — — — Power (+3.3V)
69 VSS VSS — — — — — GND
70 AVSS AVSS — — — — — Analog ref. GND for A/D conversion, GND
71 Vref− Vref− — — — — — Analog ref. V for A/D conversion, GND
72 P80 DFLG12 I/O — Pu — H DSP1 general flag 2
73 P81 DFLG11 I/O — Pu — H DSP1 general flag 1
74 P82 DR_/W1 O — — H — DSP1 interface send/receive select signal
75 P83 DACK1_ I — Pu H H DSP1 interface ACK
76 P84 DBSY1_ I — Pu H H DSP1 interface busy signal
77 P85 DFLG10 I/O — Pu — H DSP1 general flag 0
78 P86 DREQ1_ O — (Pu) H H DSP1 interface request signal
79 P87 DR_/W2 O — — H — DSP2 interface send/receive select signal
80 PD4 DACK2_ I — Pu H H DSP2 interface ACK
81 PD5 DBSY2_ I — Pu H H DSP2 interface busy signal
82 P90 DFLG20 I/O — Pu — H DSP2 general flag 0
83 P91 DREQ2_ O — (Pu) H H DSP2 interface request signal
84 P92 DFLG21 I/O — Pu — H DSP2 general flag 1
85 P93 DFLG22 I/O — Pu — H DSP2 general flag 2
86 Vref+ Vref+ — — — — — Analog ref. V for A/D conversion, +3.3V
87 AVDD AVDD — — — — — Power (+3.3V)