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DN-HS5500
D710E001ZDH300 Terminal Function
Pin No. Pin Name Symbol I/O DET Ext Ini Res Function
1A1 D_GND -----GND
2 A2 DVDH I - - - - I/O supply (+3.3V)
3 A3 AFSX0 I/O - - - - DALRCK
4 A4 ACLKX0 I/O - McASPO transmit bit clock
5A5 ACLKR0 - - Pd - -
6 A6 AXR0[14] I/O - - - - BSPDIF
7A7 D_GND -----GND
8 A8 AXR0[11] - - Pd - -
9 A9 AXR0[9] - - Pd - -
10A10 D_GND -----GND
11 A11 AEMXA1 - - Pd - -
12 A12 AXR0[4] - - Pd - -
13 A13 AXR0[2] - - Pd - -
14 A14 AXR0[0] I/O - - - - DATA_A
15 A15 DVDH I - - - - I/O supply (+3.3V)
16A16 D_GND -----GND
17 B1 DVDH I - - - - I/O supply (+3.3V)
18 B2 /UHPI_HBE3 I/O - Pu - - Byte enable signal (D31~D24)
19 B3 AD384FS - - Pd - -
20 B4 AFSR0 - - Pd - -
21 B5 AXR0[15] I/O - - - - ASPDIF
22 B6 ADDATA - - Pd - -
23 B7 AXR0[12] - - Pd - -
24 B8 AXR0[10] - - Pd - -
25 B9 AEMXA3 - - Pd - -
26 B10 AEMXA2 - - Pd - -
27 B11 AEMXA0 - - Pd - -
28 B12 AXR0[3] - - Pd
29 B13 AXR0[1] I/O - - - - DATA_B
30 B14 SPI0_SOMI I/O - I2C Serial data
31 B15 SPI0_SIMO - - Pd - - Not used
32 B16 DVDH I - - - - I/O supply (+3.3V)
33 C1 AMUTE0 - - Pd - -
34 C2 384FS - - Pd - - Not used
35 C3 - Not used
36 C4 /UHPI_HBE2 - Byte enable signal (D23~D16)
37 C5 DSPHBE - Byte enable signal (D15~D8)
38 C6 DSPHBE - Byte enable signal (D7~D0)
39 C7 DSPHWE I - - - - Write enable signal
40 C8 710HCS I - - - - Chip select signal
41 C9 /UHPI_HAS I - Pu - - Address strobe signal
42 C10 DSPHCTL1 I - - - - Control inputs select access mode (1)
43 C11 AFSX2 - - Pd - -
44 C12 AFSR2 - - Pd - -
45 C13 ACLKR2 - - Pd - -
46 C14 AHCLKR2 - - Pd - -
47 C15 /SPI0_SCS I/O - Pd - - SPI0 slave chip select
48 C16 SPI0_CLK I/O - I2C serial clock
49 D1 AHCLKX1 - - Pd - -
50 D2 AMUTE1 - - Pd - -
51 D3 - Not used
52 D4 DVDH I - - - - I/O supply (+3.3V)
53 D5 DVDH I - - - - I/O supply (+3.3V)
54 D6 /UHPI_HRDY O - - - - Host ready signal
55 D7 DSPHRD I - - - - Read strobe signal
56 D8 DSPRW I - - - - Read/not write signal
57 D9 DSPHCTL0 I - - - - Control input select access mode (0)
58 D10 AMUTE2 O - DSP interrupt
59 D11 ACLKX2 - - Pd - - McASP2 transmit bit clock
60 D12 DVDH I - - - - I/O supply (+3.3V)
61 D13 DVDH I - - - - I/O supply (+3.3V)
62 D14 EM_WAIT I - Pu - - Not used (Asynchronous wait input)
63 D15 AFMOE O - Pd - - Not used (External memory out put enable)
64 D16 /SPI0_/ENA I/O - Pd - - Not used
65 E1 ADBCK - - Pd - -
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