Denon DN-HS5500 - 15 MIRROR MIX FUNCTION

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DN-HS5500
EP2C5Q208C8N (IC103)
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EP2C5Q208C8N Terminal Function
Pin No Pin name I/O Pol Function
1 SH_DB27 IO 32 bits data bus (CPU)
2 SH_DB28 IO 32 bits data bus (CPU)
3 SH_DB29 IO 32 bits data bus (CPU)
4 SH_DB30 IO 32 bits data bus (CPU)
5 SH_DB31 IO 32 bits data bus (CPU)
6 SH_RD I N (CPU: -RD)
7 VCCIO1 VCCIO1
8 PS2DAT OUT O PS/2 data output (Not used)
9GND GND
10 PS2_INH O N PS/2 inhibit signal output (Not used)
11 PS2_PWR O PS/2 Power ON/_OFF signal (Not used)
12 SH_CS5 I N LCD, 32 bits bus width (CPU)
13 SH_IRQa O Interrupt request 2 (CPU:PINT2)
14 SHAD_TRG O N Non-maskable interrupt request (CPU:NMI)
15 SH_IRQb O Interrupt request 3 (CPU:IRQ1)
16 TDO TDO
17 TMS TMS
18 TCK TCK
19 TDI TDI
20 DATA0 DATA0 Configuration (CPU:TxD2)
21 DCLK DCLK Configuration (CPU:SCK2)
22 nCE nCE GND
23 SH_CKIO I Master clock: 67.7MHz (CPU:CKIO)
24 SH_CS6 I N TMS32DA710, 16 bits bus width (CPU)
25 GND GND
26 nCONFIG nCONFIG Configuration (CPU:PE1)
27 PS2DAT I PS/2 data input (Not used)
28 PS2CLK I PS/2 clock (Not used)
29 VCCIO1 VCCIO1
30 LCD_SYNC O Send LCD reading start trigger to CPU (CPU:IRQ0)
31 SH_RDY O Wait (CPU:-WAIT)
32 SCL IO N IIC clock line L
33 SH_BS I N (CPU:-BS)
34 SH_DRQ O DMA transfer request (CPU:DRQ0)
35 SH_IRQc O Interrupt request 3 (PS/2 to CPU:PINT3)
36 SH_CS7 I N LCD, IDE, PANEL, PS/2, FPGA 32 bits bus width (CPU)
37 SH_DAK I DMA transfer accept (CPU:DACK0)
38 GND GND