Epson S1C6200A - Page 19

S1C6200/6200A CORE CPU MANUAL EPSON 13
2 MEMORY AND OPERATIONS
Fig. 2.5.3.1 Interrupt timing during execution
Clock
Status
Instruction
Fetch
5-clock Instrruction
Interrupt
INT1 (*1) INT2 (*1) JP (*2)
12-clock instruction
7-clock instruction
5-clock instruction
... 13 to 25 clock cycles
... 13 to 20 clock cycles
... 13 to 18 clock cycles
Interrupt processing:
S1C6200
Clock
Status
Instruction
5-clock Instrruction
Interrupt
INT1 (*1) INT2 (*1) JP (*2)
12-clock instruction
7-clock instruction
5-clock instruction
... 12.5 to 24.5 clock cycles
... 12.5 to 19.5 clock cycles
... 12.5 to 17.5 clock cycles
Interrupt processing:
S1C6200A
Execute Note: (*1)
(*2)
INT1 and INT2 are dummy instructions
Branches to the top of the interrupt service routine
Status:
12-clock Instrruction
12-clock Instrruction
Fig. 2.5.3.2 Interrupt timing in the HALT mode
Fetch
System clock
CPU clock
Status
Instruction
5-clock Instrruction
Interrupt
INT1 (*1) INT2 (*1) JP (*2)
Interrupt processing: 14 to 15 clock cycles
S1C6200/6200A
Execute Note: (*1)
(*2)
INT1 and INT2 are dummy instructions
Branches to the top of the interrupt service routine
Status:
HALT