Epson S1C6200A - Page 20

14 EPSON S1C6200/6200A CORE CPU MANUAL
2 MEMORY AND OPERATIONS
Fig. 2.5.3.3 Interrupt timing in SLEEP mode
Fig. 2.5.3.4 Interrupt timing with PSET
Fetch
System clock
CPU clock
Status
Instruction
5-clock Instrruction
Interrupt
INT1 (*1) INT2 (*1) JP (*2)
Interrupt processing: 14 to 15 clock cycles
S1C6200/6200A
Execute Note: (*1)
(*2)
INT1 and INT2 are dummy instructions
Branches to the top of the interrupt service routine
Status:
SLEEP
Clock
Status
Instruction
Fetch
PSET
Interrupt
INT1 (*1) INT2 (*1) JP (*2)
PSET + CALL
PSET + JP
... 13 to 25 clock cycles
... 13 to 23 clock cycles
Interrupt processing:
S1C6200
Clock
Status
Instruction
PSET
Interrupt
INT1 (*1) INT2 (*1) JP (*2)
PSET + CALL
PSET + JP
... 12.5 to 24.5 clock cycles
... 12.5 to 22.5 clock cycles
Interrupt processing:
S1C6200A
Execute Note: (*1)
(*2)
INT1 and INT2 are dummy instructions
Branches to the top of the interrupt service routine
Status:
CALL
CALL