Epson S1C6200A - Page 37

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 31
3 INSTRUCTION SET
ADC YH,i Add with carry immediate data i to YH
ADC YH,i
YH ← YH + i
3 to i0 + C
10100010i
3 i2 i1 i0 A20H to A2FH
IV
7
Set if a carry is generated; otherwise, reset.
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Adds the carry bit and immediate data i to YH, the four high-order bits of YHL.
ADC YH,3 ADC YH,6
YH register 1010 1110 0100
C flag 1 0 1
Z flag 0 0 0
ADC YL,i Add with carry immediate data i to YL
ADC YL,i
YL ← YL + i
3 to i0 + C
10100011i
3 i2 i1 i0 A30H to A3FH
IV
7
Set if a carry is generated; otherwise, reset.
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Adds the carry bit and immediate data i to YL, the four low-order bits of YHL.
ADC YL,3 ADC YL,2
YL register 1010 1110 0000
C flag 1 0 1
Z flag 0 0 1