Epson S1C6200A - Page 38

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
32 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
ADD r,i Add immediate data i to r-register
ADD r,i
r ← r + i
3 to i0
110000r1 r0 i3 i2 i1 i0 C00H to C3FH
II
7
Set if a carry is generated; otherwise, reset.
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Adds immediate data i to the contents of the r-register.
ADD A,5 ADD MY,2
A register 1010 1111 1111
Memory (MY) 0110 0110 1000
C flag 1 0 0
Z flag 0 0 0
ADD r,q Add q-register to r-register
ADD r,q
r ← r + q
10101000r1 r0 q1 q0 A80H to A8FH
IV
7
Set if a carry is generated; otherwise, reset.
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Adds the contents of the q-register to the contents of the r-register.
ADD A,MY ADD MX,B
A register 0010 1111 1111
B register 0100 0100 0100
Memory (MX) 0111 0111 1011
Memory (MY) 1101 1101 1101
C flag 1 0 0
Z flag 1 0 0