Epson S1C6200A - Page 56

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
50 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LDPY MY,i Load immediate data i into MY, increment Y by 1
LDPY MY,i
M(Y) ← i
3 to i0, Y ← Y + 1
11100111 i
3 i2 i1 i0 E70H to E7FH
IV
5
Not affected
Not affected
Not affected
Not affected
Loads immediate data i into the data memory location addressed by IY. Y is
incremented by 1. Incrementing Y does not affect the flags.
LDPY MY,7 LDPY MY,0
Y register 0010 1101 0010 1110 0010 1111
Memory (2DH) 1010 0111 0111
Memory (2EH) 0010 0010 0000
LDPY r,q Load q-register into r-register, increment Y by 1
LDPY r,q
r ← q, Y ← Y + 1
11101111 r1 r0 q1 q0 EF0H to EFFH
IV
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the q-register into the r-register. Y is incremented by 1.
Incrementing Y does not affect the flags.
LDPY A,B LDPY MX,B
Y register 0100 1000 0100 1001 0100 1010
A register 1010 1000 1000
B register 1000 1000 1000
Memory (MX) 0010 0010 1000