Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 51
3 INSTRUCTION SET
LD r,i Load immediate data i into r-register
LD r,i
r ← i
3 to i0
111000r1 r0 i3 i2 i1 i0 E00H to E3FH
II
5
Not affected
Not affected
Not affected
Not affected
Loads immediate data i into the r-register.
LD A,6 LD MY,0
A register 0101 0110 0110
Memory (MY) 1001 1001 0000
LD r,q Load q-register into r-register
LD r,q
r ← q
11101100r1 r0 q1 q0 EC0H to ECFH
IV
5
Not affected
Not affected
Not affected
Not affected
The contents of the q-register are loaded into the r-register.
LD A,B LD B,MY
A register 0010 0000 0000
B register 0000 0000 0110
Memory (MY) 0110 0110 0110
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