Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
52 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD r,SPH Load SPH into r-register
LD r,SPH
r ← SPH
1111111001r1 r0 FE4H to FE7H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the four high-order bits of the stack pointer into the r-register.
LD MX,SPH LD A,SPH
SPH 0111 0111 0111
A register 0000 0000 0111
Memory (MX) 1100 0111 0111
LD r,SPL Load SPL into r-register
LD r,SPL
r ← SPL
1111111101r1 r0 FF4H to FF7H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the four low-order bits of the stack pointer into the r-register.
LD A,SPL LD MY,SPL
SPL 1001 1001 1001
A register 0010 1001 1001
Memory (MY) 0000 0000 1001
To Next Page
Loading...
