Epson S1C6200A - Page 59

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 53
3 INSTRUCTION SET
LD r,XH Load XH into r-register
LD r,XH
r ← XH
1110101001r1 r0 EA4H to EA7H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the four high-order bits of register X into the r-register.
LD B,XH LD MX,XH
XH register 1010 1010 1010
B register 0010 1010 1010
Memory (MX) 0000 0000 1010
LD r,XL Load XL into r-register
LD r,XL
r ← XL
1110101010r1 r0 EA8H to EABH
V
5
Not affected
Not affected
Not affected
Not affected
Loads the four low-order bits of register X into the r-register.
LD MY,XL LD A,XL
XL register 0000 0000 0000
A register 1101 1101 0000
Memory (MY) 0001 0000 0000