Epson S1C6200A - Page 60

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
54 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD r,XP Load XP into r-register
LD r,XP
r ← XP
1110101000r1 r0 EA0H to EA3H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the 4-bit page part of index register IX into the r-register.
LD MX,XP LD A,XP
XP register 1111 1111 1111
A register 0010 0010 1111
Memory (MX) 0101 1111 1111
LD r,YH Load YH into r-register
LD r,YH
r ← YH
1110101101r1 r0 EB4H to EB7H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the four high-order bits of register Y into the r-register.
LD A,YH LD MY,YH
YH register 1010 1010 1010
A register 1100 1010 1010
Memory (MY) 1110 1110 1010