Epson S1C6200A - Page 61

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 55
3 INSTRUCTION SET
LD r,YL Load YL into r-register
LD r,YL
r ← YL
1110101110r1 r0 EB8H to EBBH
V
5
Not affected
Not affected
Not affected
Not affected
Loads the four low-order bits of register Y into the r-register.
LD B,YL LD MX,YL
YL register 0000 0000 0000
B register 0110 0000 0000
Memory (MX) 1011 1011 0000
LD r,YP Load YP into r-register
LD r,YP
r ← YP
1110101100r1 r0 EB0H to EB3H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the 4-bit page part of index register IY into the r-register.
LD MY,YP LD B,YP
YP register 1010 1010 1010
B register 1100 1100 1010
Memory (MY) 0110 1010 1010