Epson S1C6200A - Page 62

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
56 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD SPH,r Load r-register into SPH
LD SPH,r
SPH ← r
1111111000r1 r0 FE0H to FE3H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the r-register into the four high-order bits of the stack
pointer.
LD SPH,A LD SPH,MY
SPH 1001 0011 1100
A register 0011 0011 0011
Memory (MY) 1100 1100 1100
LD SPL,r Load r-register into SPL
LD SPL,r
SPL ← r
1111111100r1 r0 FF0H to FF3H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the r-register into the four low-order bits of the stack pointer.
LD SPL,B LD SPL,MX
SPL 1011 0111 1111
B register 0111 0111 0111
Memory (MX) 1111 1111 1111