Epson S1C6200A - Page 63

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 57
3 INSTRUCTION SET
LD X,e Load immediate data e into X-register
LD X,e
XH ← e
7 to e4, XL ← e3 to e0
1011e7 e6 e5 e4 e3 e2 e1 e0 B00H to BFFH
I
5
Not affected
Not affected
Not affected
Not affected
Loads 8-bit immediate data e into register X.
LD X,6FH
XH register 0000 0110
XL register 1011 1111
LD XH,r Load r-register into XH
LD XH,r
XH ← r
1110100001r1 r0 E84H to E87H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the r-register into the four high-order bits of register X.
LD XH,A LD XH,MY
XH register 0000 1011 0110
A register 1011 1011 1011
Memory (MY) 0110 0110 0110