Epson S1C6200A - Page 64

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
58 EPSON S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
LD XL,r Load r-register into XL
LD XL,r
XL ← r
1110100010r1 r0 E88H to E8BH
V
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the r-register into the four low-order bits of register X.
LD XL,MY LD XL,A
XL register 0000 0010 1011
A register 1011 1011 1011
Memory (MY) 0010 0010 0010
LD XP,r Load r-register into XP
LD XP,r
XP ← r
1110100000r1 r0 E80H to E83H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the r-register into the 4-bit page part of index register IX.
LD XP,B LD XP,MX
XP register 1001 0001 1011
B register 0001 0001 0001
Memory (MX) 1011 1011 1011