Eventide Ultra-Harmonizer H3000 - Page 6

Delay Memory
The
delay
memory
is
a
64
K
word
block
of
memory
that
is
used
to
create
audio
delay
lines.
64
k
by
4-bit
dynamic
RAMs
are
used
for
this.
The
delay
memory
cycle
time
is
once
every
two
processor
cycles.
Since
the
TMS32010
has
only
a
4
K
word
external
address
space
(and
this
is
limited
to
program
memory
only),
special
hardware
is
used
to
address
the
delay
memory.
The
delay
memory
is
accessed
through
two
separate
ports
on
the
global
bus.
One,
the
Delay
Address
Register,
is
a
sixteen
bit
fegister
that
controls
the
address
of
the
next
delay
memory
cycle.
The
other,
the
Delay
Data
Register,
is
used
to
read
or
write
data
to
the
delay
memory.
Thus,
reading
from
or
writing
to
the
delay
memory
requires
two
global
bus
accesses,
the
first
to
specify
the
address
and
the
second
to
actually
read
or
write
the
data.
In
order
to
ease
the
I/O
trouble
of
delay
accesses,
the
Delay
Address
Register
is
equipped
with
a
set
of
counters.
Each
time
a
read
is
completed
from
the
delay
memory,
the
address
register
is
incremented,
allowing
successive
locations
to
be
read
more
efficiently.
Analog
Input
and
Output
The
audio
input
is
provided
by
a
two
channel,
16-bit
analog
to
digital
converter,
sampling
at
a
rate
of
44.1
kHz.
The
two
channels
of
data,
multiplexed
in
time,
are
available
at
the
same
address
on
the
global
bus.
The
tight
channel’s
data
is
available
during
the
first
half
of
the
sample
period
and
the
left
channel's
data
is
available
during
the
other.
The
audio
data
is
re-converted
to
analog
by
two
16-bit
digital
to
analog
converters.
The
left
and
right
D/A
converters
each
have
their
own
address
on
the
global
bus.
The
converters
can
be
set
to
run
at
the
input
sample
rate
of
44.1
kHz
(synchronous),
or
at
a
variable
sample
rate
(asynchronous).
The
variable
sample
rate
is
provided
in
order
to
allow
pitch
shifting
without
the
need
tor
digital
decimation/interpolation
filters,
The
variable
output
sample
rate
is
provided
by
a
pair
of
frequency
synthesizers.
А
40
MHz
clock
is
divided
down
to
provide
an
output
sample
rate
that
can
vary
from
22
kHz
to
88
kHz.
The
control
inputs
to
the
frequency
synthesizers
are
available
on
the
global
bus,
and
thus
can
be
controlled
by
the
PELs
or
by
the
host
processor.
On
each
new
output
clock
cycle,
the
frequency
synthesizers
set
status
bits
to
indicate
that
data
is
needed
for
the
D/A
converters.
These
bits
can
be
read
and
tested
by
the
PELs.
The Status Port
The
status
port
is
sort
of
the
catch-all
location
in
the
bus
design.
A
read
of
the
status
port
returns
the
values
of
a
number
of
one-bit
flags
in
the
system.
Some
are
general
purpose
bits,
intended
for
handshaking
and
triggering
events.
Others
are
special
purpose,
including
the
Odd/Even
Sync
bit
(explained
under
Synchronization),
and
the
frequency
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