Eventide Ultra-Harmonizer H3000 - Page 7

synthesizer
status
bits.
Writes
to
the
status
register
are
channeled
to
various
registers,
depending
upon
the
value
in
the
upper
4
bits
of
the
data
word.
The
possible
destinations
include
the
bit
registers
mentioned
above,
the
frequency
synthesizer
control
words,
and
interrupt
lines
for
both
the
host
processor
and
the
PELs.
Bus Allocation
Global
bus
cycle
allocation
is
based
around
the
input
sample
period.
Each
22
microsecond
sample
period
is
evenly
divided
into
104
time
slots,
each
slot
corresponding
to
an
available
bus
cycle.
One
bus
cycle
per
sample
period
is
reserved
for
the
host
processor,
leaving
103
cycles
available
for
the
PELs.
Also,
the
delay
memory
is
unavailable
for
4
time
slots
per
sample
period,
due
to
the
refresh
needs
of
its
dynamic
RAM.
Bus
contention
will
result
if
any
two
PELs
access
the
global
bus
simultaneously,
and
is
to
be
avoided.
There
is
an
exception
to
this
rule,
though.
Two
or
more
processors
can
access
the
bus
simultaneously
if
they
are
reading
from
the
same
device.
This
is
particularly
useful
for
reading
data
from
the
A/D
converters
and
for
reading
from
the
host
interface
registers.
Synchronization
The
bus
design
makes
processor
synchronization
a
crucial
issue.
Synchronization
in
this
architecture
takes
place
on
several
levels.
The
first
and
lowest
level
of
synchronization
is
PEL
syne,
the
synchronization
of
the
internal
states
of
the
TMS32010
processors.
The
TMS32010
has
four
possible
internal
states.
In
order
for
multiple
processors
to
access
the
same
bus,
these
states
must
be
synchronized.
As
with
the
host
interface,
the
TMS32010
has
no
convenient
way
of
doing
this.
To
circumvent
this
problem
a
circuit
which
Compares
the
output
clock
of
the
TMS32010
with
a
reference
clock
is
used,
if
the
two
clocks
are
out
of
phase,
this
circuit
eliminates
one
input
clock
period
to
the
TMS32010.
Ciock
periods
are
dropped
until
the
two
clocks
are
in
phase.
By
applying
this
circuit
to
all
of
the
PELs,
synchronization
between
the
processors
is
automatically
maintained.
The
highest
level
of
synchronization
is
sample
period
sync.
Since
bus
cycle
allocation
is
based
on
the
sample
period,
each
processor
must
know
where
it
is
in
relation
to
the
sample
clock.
The
TMS32010
has
an
input
pin,
BIO,
specifically
for
this
purpose.
The
BIO
pin
is
a
one
bit
input
which
can
be
used
as
a
branch
condition
by
the
processor.
In
order
to
synchronize
with
the
start
of
a
sample
period,
the
processor
simply
waits
for
the
state
of
the
BIO
pin
to
change.
There
is
one
final
level
of
synchronization.
Since
the
BIO
input
to
the
PELs
is
sampled
only
every
other
instruction,
there
is
a
one
cycle
uncertainty
in
synchronization.
To
eliminate
this
uncertainty,
a
middle
level
of
Synchronization,
ODD/EVEN
sync
is
provided.
One
of
the
bits
in
the
status
port
gives
an
indication
of
whether
the
processor
is
on
an
odd
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