System Hardware Installation
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3-5-4 Processor and Memory Module Matrix Table
4 DIMM
Memory Q’ty
for each CPU
CPU1
J0 I0 L0 K0 O0 P0 M0 N0
V
1 DIMM
2 DIMM
6 DIMM
8 DIMM
V
V V
VVVV
V VV
V
V
V
VVVV
V VV
CPU0
B0 A0 D0 C0 G0 H0 E0 F0
V
V V
VVVV
VV V V VVV
V V V V V V
V
NOTE!
l
There should be at least one DDR4 DIMM per socket.
l
If only one DIMM is populated in a channel, then populate it in the slot furthest away from CPU of that channel.
l
Channel 0's on each memory controller (A/E/C/G, I/M/K/O) must be populated with same total capacity per channel
(if populated).
l
Channel 1's on each memory controller (B/F/D/H, J/N/L/P) must be populated with same total capacity per channel
(if populated).