Gigabyte G492-ZD0 - Page 98

BIOS Setup - 98 -
Parameter
Description
Target Static Lane Select
Upper 32 bits
This item is congurable when Target Static Lane Control is set to
Enabled.
Target Static Lane Select
Lower 32 bits
This item is congurable when Target Static Lane Control is set to
Enabled.
Target Static Lane Select
ECC
This item is congurable when Target Static Lane Control is set to
Enabled.
Target Static Lane Value
This item is congurable when Target Static Lane Control is set to
Enabled.
Data Eye Type
This item determines which results are expected to be captured for Data Eye.
Options available: 1D Voltage Sweep, 1D Timing Sweep, 2D Full Data Eye,
Worst Case Margin Only. Default setting is Worst Case Margin Only.
Worst Case Margin
Granularity
Congures Worst Case Margin Granularity.
Options available: Per Chip Select, Per Nibble.
Default setting is Worst Case Margin Only.
Read Voltage Sweep Step
Size
Congures the step size for read Data Eye voltage sweep.
Options available: 1, 2, 4. Default setting is 2.
Read Timing Sweep Step
Size
Congures the step size for read Data Eye timing sweep.
Options available: 1, 2, 4. Default setting is 1.
Write Voltage Sweep Step
Congures the step size for write Data Eye voltage sweep.
Options available: 1, 2, 4. Default setting is 2.
Write Timing Sweep Step
Size
Congures the step size for write Data Eye timing sweep.
Options available: 1, 2, 4. Default setting is 1.