MK2302S-01
MDS 2302S-01 B
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
Multiplier and Zero Delay Buffer
Description
The MK2302S-01is a high performance Zero Delay
Buffer (ZDB) which integrates ICS’ proprietary
analog/digital Phase Locked Loop (PLL) techniques.
The chip is part of ICS’ ClockBlocks
TM
family and was
designed as a performance upgrade to meet today’s
higher speed and lower voltage requirements. The zero
delay feature means that the rising edge of the input
clock aligns with the rising edges of both output clocks,
giving the appearance of no delay through the device.
There are two outputs on the chip, one being a
low-skew divide by two of the other output.
The MK2302S-01 is ideal for synchronizing outputs in a
large variety of systems, from personal computers to
data communications to graphics/video. By allowing
off-chip feedback paths, the device can eliminate the
delay through other devices.
Features
• 8 pin SOIC package
• Low input to output skew of 250ps max
• Absolute jitter ± 500ps
• Propagation Delay ± 350ps
• Ability to choose between different multipliers from
0.5X to 16X
• Output clock frequency up to 133 MHz at 3.3V
• Can recover degraded input clock duty cycle
• Output clock duty cycle of 45/55
• Full CMOS clock swings with 25mA drive capability
at TTL levels
• Advanced, low power CMOS process
• Operating voltage of 3.3V or 5V
• Industrial temperature version available
Block Diagram
Phase
Detector,
Charge
Pump,
and Loop
Filter
divide
by N
CLK1
External feedback can come from CLK1 or CLK2 (see table on page 2)
ICLK
FBIN
S1:0
VCO
CLK2
/2
AVR3600 harman/kardon
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