MDS 2302S-01 B
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
FBIN
ICLK
GND
VDD
S0
CLK1
CLK21
2
3
4
8
7
6
5
GND
S1
1
2
3
4
8
7
6
5
8 pin (150 mil) SOIC
FBIN S1 S0 CLK1 CLK2
CLK1 0 0 2 X ICLK ICLK
CLK1 0 1 4 X ICLK 2 X ICLK
CLK1 1 0 ICLK ICLK/2
CLK1 1 1 8 X ICLK 4 X ICLK
CLK2 0 0 4 X ICLK 2 X ICLK
CLK2 0 1 8 X ICLK 4 X ICLK
CLK2 1 0 2 X ICLK ICLK
CLK2 1 1 16 X ICLK 8 XICLK
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 FBIN Input Feedback clock input.
2 ICLK Input Reference clock input.
3 GND Power Connect to ground.
4 S0 Input Select 0 for output clock per decoding table above. Pull-up.
5 S1 Input Select 1 for output clock per decoding table above. Pull up.
6 CLK1 Output Clock output per table above.
7 VDD Power Connect to +3.3V or +5.0V.
8 CLK2 Output Clock output per table above. Low skew divide by two of pin 6 clock.