Hitachi AP1 - Page 175

----------------------------------LCD-III
Date
I LCD·III M •• k Option List I
ROM CODE 10
Customer's Name
Hitachi
PIN
(1) I/O Option
Pin Name
I/O
I/O Option
Remarks
Pin Name
I/O
I/O Option
Remarks
A
B C
A
B C
Do
I/O
Roo
I
-----
01
I/O
ROl
I
------
Dl I/O
R02
I
-----
03
I/O
R03 I
--
D4
I/O
RIO I/O
05
I/O
Rll I/O
06
I/O
Rll I/O
07
I/O
RI3 I/O
Os
I/O
R20
I/O
09
I/O
Rll
I/O
010
I/O
R22
I/O
011
I/O
R23 I/O
Oil I/O
Rla
0
----
013
I/O
R31
0
----
014
I/O
R32
0
---
015 I/O
R33
0
-----
INTo
I
~
INTI
I
---
• Specify the I/O composition with a mark of "0" in the applicable composition column.
A: No pull up MOS B: With pull up MOS C: CMOS Output
(2) Oscillator & External Halt
~
Not used
Used (Reset
is applied when Halt release)
Used (Reset is not applied when Halt release)
Oscillator
Resistor
Ceramic Resonator
External Clock
·Please check one section on the above chart.
(3) Oscillator & Internal Halt
~
No (RAM contents are
No (RAM
contents are
Yes
(It is provided only
Halt
not kept by reset)
kept by reset)
when
the crystal for timer exists.)
Oscillator
Resistor
Ceramic Resonator
----===
External Clock
• Please check one section on the above chart.
(4) Other Options
I/O
State at Halt Mode o Enable o Disable
External Crystal
for Timer
0
Yes
0
No
Jf
"Yes", 0
14
and 015 become XO andXI
for connection of Crystal. Therefore, no 1/0
option can be selectable.
Supply Voltage
0
5 ±O.5V
0
2.7 to 5.5V
• Mark ".j" in "0" for the selected I/O state.
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