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Hitachi AP1 - Page 51

Hitachi AP1
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--------------------------------------------------------HMCS44C,HMCS44CL
'"
X
0
.-
N
M
.q-
It)
co
,...
.-
.-
I
00
Ln
.-
I
N
....
y
~
0
.-
N
M
.q-
It)
co
,...
00
C1>
i
file No.
15
14
13
12
11
15
14
13
12
11
LO
.q-
M
N
.-
~
~
~
~
~
~
~
~
~
~
10
9 8
7 6 5
4
3
2
1
0
10
9 8
7
6
5 4 3
2 1
'0
+-
digit No.
0
~
C1>
00
,...
co
LO
.q-
M
N
~
0
a:
a:
a:
a:
a:
a:
a:
a:
a:
~
~
~
~
~
~
~
~
~
~
~
* The file 8 is selected when X register
has
any value in 8
to
11, and the file
9
is
selected when 12
to
15.
M(O)
o
M(l)
o 2
M(2)
10
3
M(3)
n=Bit
assignmen No.
Figure
10
RAM Address Space
REGIS:TER
The ,HMCS44C has six 4-bit registers and two I-bit registers
available to the programmer. The I-bit registers are the Carry
FI
F and the Status
F/F.
They are explained in the following para-
graphs.
Status
F/F (S)
The Status FIF latches the result of
logical
or arithmetic oper-
ations (Not Zero, Overflow) and bit test operations. The Status
F/F affects conditional instructions (LPU,
DR
and CAL instruc-
tions). These instructions are executed
only
when the Status FIF
is
"1".
If
it
is
"0",
these instructions are skipped and the Status
F/F
becomes
"I".
Figure
11
RAM Bit and Operand n
49